I’m encountering an issue with configuring GPIOs using the Jetson_Orin_NX_and_Orin_Nano_series_Pinmux_Config_Template.xlsm spreadsheet for my custom project. Specifically, I’m trying to configure GPIO04 and GPIO05 as outputs and toggle their values, but I’m unable to map them correctly to the GPIO space or control them as expected.
Here’s a brief overview of the issue:
I used the provided spreadsheet tool to define the GPIO configuration and exported the DTSI files.
I’m working with GPIO04 (line 127) and GPIO05 (line 128), but I can’t seem to toggle their values, and they don’t appear to respond as expected.
I’ve confirmed that the DTSI files generated by the spreadsheet are loaded, but the GPIOs are not behaving as intended.
Could someone help me understand how the GPIO mapping works in this case and why I might be having trouble controlling these pins?
For reference, here are the links to the spreadsheet and the DTSI files:
Jetson Orin NX and Orin Nano Series Pinmux Config Template
https://www.dropbox.com/scl/fi/6007ruxmsrz69xit5mwox/Jetson_Orin_NX_and_Orin_Nano_series_Pinmux_Config_Template__os1__.xlsm?rlkey=ba9gvnbths8ukgipo6z0nep4p&st=49e5kt08&dl=0
DTSI files (cernis)
https://www.dropbox.com/scl/fi/4sq9vt7s1r26mwuuhmomc/dtsi_cernis.tar?rlkey=imd69jv1svfm92snrt9dx7f1j&st=d4mibgyw&dl=0
Any guidance or insights on how to resolve this issue would be greatly appreciated!
I cannot control PCC.01. Although it shows as an output, it doesn’t change values when toggled. I verified this via readback and voltage measurement. gpioinfo states that PCC.01 is on gpiochip1 pin 13, while the spreadsheet states that this same GPIO is on gpiochip0 pin 127. I’m not sure what to make of that.
Could you pull this code, look through it, and see if the patch you mentioned would work? I don’t see how it would, but perhaps there’s a way to make the change outlined in the patch work.
I don’t see any reference to tegra_pinctrl_soc_data in my entire codebase. Could I be missing something. Do I need to do a menuconfig type thing to pull in this level of GPIO control?
Bootload change to disable EEPROM check in MB1 bootloader
cd ./R36.4.0/Linux_for_Tegra/bootloader/.
find . -type f -exec sed -i ‘s/cvb_eeprom_read_size = <0x100>/cvb_eeprom_read_size = <0x0> /*(FiSH)*//g’ {} +
cd …
Pull kernel code
cd ./source
./source_sync.sh -k -t jetson_36.4
Apply patch to fix GPIO assignments
cd ./kernel/kernel-jammy-src/
sudo git apply …/…/…/…/…/40hdr_SPI1_gpio_padctl_register_bit10_effect_by_gpiod_tools_in_JP6.patch
cd …/…
Make kernel and dtb
export CROSS_COMPILE=/opt/nvidia/toolchain/aarch64–glibc–stable-2022.08-1/bin/aarch64-buildroot-linux-gnu-
export KERNEL_HEADERS=$(pwd)/kernel/kernel-jammy-src
make -C kernel
export INSTALL_MOD_PATH=$(pwd)/…/rootfs
sudo -E make install -C kernel
Make device tree blob
cp kernel/kernel-jammy-src/arch/arm64/boot/Image …/kernel/Image
make dtbs
cp kernel-devicetree/generic-dts/dtbs/* …/kernel/dtb/.
cd …
Flash to device which needs to be in recovery mode