I’m developing a motherboard compatible with TX2 NX, Xavier, and Nano, and I’m trying to wire up an eMMc in my schematic. I’m a bit confused about the eMMc running in HS400 mode. Here are a few questions:
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My eMMc has 8 data lines, but the TX2 for example only has 4. Can the eMMc still run in HS400 mode? As per the 5.1 standard does it require all of the pins to function?
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There is a Data Strobe pin on my eMMc, but I do not see this on the TX2 NX pinout. I thought that Data Strobe was required for the eMMc to function in HS400 mode.
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Apparently, the eMMc defaults to HS400 mode, and I’m wondering if there’s something in the 5.1 standard that says if it tries to work in this mode but is unsuccessful, it will try to run in different modes until it works.
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As for general circuit design, I saw some people online put some ESD protection on the data, cmd, and clk lines. Do you think this is a good idea or would just affect the emi performance?
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I saw online as well that most people put 10k pull ups on all the data and cmd lines, but not the clk. Would someone agree that the clk doesn’t need a 10k pullup?
New to this so I’m not 100% how user-friendly the eMMc standard is.
I can say that the eMMc is a Flexxon ECON II Series 64GB eMMc, but I can’t share the datasheet unfortunately due to an NDA.