Hello,
We are currently assisting a client with a 5G/RAN project on the Jetson Thor (Blackwell) platform. We need to verify the configuration steps for high-speed data ingestion and processing using the Aerial CUDA-accelerated RAN libraries.
Need guidance or reference documentation for the following:
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QSFP28 Link Bring-up: What is the procedure to enable the 40G/100G link on the Thor board? Specifically, are there updated device tree settings or firmware requirements to support 100G when connected to an external FPGA peer?
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Aerial SDK Compatibility: Is there a specific release of the Aerial SDK or a “Getting Started” guide optimized for the Thor Blackwell architecture? We want to ensure the client is using the correct CUDA-accelerated L1/L2 libraries for this board.
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Data Pipeline (QSFP to NVMe): The project requires logging high-speed data from the QSFP28 link directly to the NVMe storage. Are there any recommended system-level tuning steps (e.g., PCIe Gen5 settings or interrupt steering) to ensure reliable throughput for this data path?
Any technical references or pinmux guidelines for these interfaces on Thor would be very helpful.