Dear Team, We are currently developing a high-speed data interface between the Jetson Thor platform and a custom FPGA-based board using a QSFP28 (100G Ethernet) link.
On the FPGA side, the 100G interface is implemented in Vivado using the Xilinx CMAC IP core, and the design has been successfully synthesized, implemented, and programmed into the FPGA.
Target Workflow
Our intended system architecture is as follows:
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FPGA → Jetson Thor
Stream raw IQ sample data from the FPGA to Jetson Thor over the 100G QSFP28 interface. -
GPU Processing (Jetson Thor)
Perform real-time 5G Physical Layer (L1) inference directly on the GPU. -
Jetson Thor → FPGA
Send the processed results (or updated model parameters) back to the FPGA over the same QSFP28 interface, where the 5G L1 stack is running.
Technical Objective
We would like to implement this data path using GPUDirect RDMA, enabling:
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Direct data transfer from the FPGA Ethernet subsystem to GPU memory (bypassing CPU copies)
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In-GPU inference processing
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Direct transmission of processed data from GPU memory back to the FPGA
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Proper reception on the FPGA side using the Xilinx CMAC / 40G–50G Ethernet Subsystem IP
We are seeking guidance on the feasibility, required architecture, driver stack considerations, and configuration steps needed to enable GPUDirect RDMA in this setup.