Hi Team,

We are trying to check the performance(bandwidth, latency) of PCIe C5 by DMA read and write test between two AGX Orin Devkit (L4T 35.3.1) by configuring One Jetson AGX Orin as Root Complex and another Jetson AGX Orin as Endpoint.

Is there any other way to perform DMA test to analyze bandwidth, latency and other performance metrics of PCIE port c5 in Jetson ORIN with L4T35.3.1?

Previously, we did the DMA test provided in the (nvidia/drivers/pci/dwc/pcie-tegra.c) in jetpack 4.4 (kernel 4.9) for validating the performance of PCIe between two jetson AGX Xavier devkit and it was worked fine. But it was not available in current L4T.

Thanks in Advance


What is the exact problem here? You can still use same test to test DMA performance.

dwc.zip (31.0 KB)
Hi @WayneWWW
I want to try the DMA test code provided in the nvidia/drivers/pci/dwc/pcie-tegra.c.
By default, L4T 35.3.1 has no option to configure CONFIG_PCIE_TEGRA_DW_DMA_TEST to build and use nvidia/drivers/pci/dwc/pcie-tegra.c driver. Even forcefully enabling CONFIG_PCIE_TEGRA_DW_DMA_TEST leads to kernel build errors.

I have attached the driver source. In the Makefile

ccflags-y += -I$(srctree)/drivers/pci/dwc
obj-$(CONFIG_PCIE_TEGRA) += pcie-tegra.o


CONFIG_ARCH_TEGRA_19x_SOC config is required but forcefully enabling in defconfig or disabling condition “ifdef CONFIG_ARCH_TEGRA_19x_SOC” in Makefile lead to kernel dependency build errors.
For old L4T32.6.1 kernel 4.9, CONFIG_ARCH_TEGRA_19x_SOC is by default enabled in defconfig.

As this driver is not suitable for ORIN L4T35.3.1 kernel 5.10 can you suggest us alternate method to check the performance(bandwidth, latency) of PCIe C5.


please directly remove that CONFIG_ARCH_TEGRA_19x_SOC and see if it can build.

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.