Enabling SPI Nodes on Xavier-Nx

Robotics & Edge Computing Jetson & Embedded Systems Jetson Xavier NX
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1

I am trying to add these 2 SPI nodes /dev/spidev0.0 and /dev/spidev1.0 with the Device tree entries below for Xavier-Nx. I was successful in getting the nodes added, but when I run the test program spidev_test.c as a loopback (MOSI <-> MISO), it fails. The output is not the same as the input i.e. the transmitted hexadecimal array that ends with “DEAD BEEF BAAD FOOD”. The output is very often 0s and sometimes random hexadecimal values with the same array length of 38 like the input. I suspect the DT nodes are not correct for Xavier-Nx and was wondering if someone could give this a look and point me in the right direction? Please see my SPI DT nodes below as well as the pinmux cfg values. The Signal names, pin numbers and Ball names for SPI0 are:

SPI0_SCK 91 SPI1_SCK
SPI0_MISO 93 SPI1_MISO
SPI0_MOSI 89 SPI1_MOSI
SPI0_CS0 95 SPI1_CS0
SPI0_CS1 97 SPI1_CS1

spi@3210000{
status = “okay”;
spi@0 {
compatible = “spidev”;
reg = <0x0>;
spi-max-frequency = <33000000>;
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <7>;
};
};

spi@c260000 {
//status = “disabled”;
status = “okay”;
spi@0 {
compatible = “spidev”;
reg = <0x0>;
spi-max-frequency = <33000000>;
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <6>;
};
};

spi@3300000 {
status = “disabled”;
};

spi@3230000{
status = “okay”;

            };

spi@3230000{
status = “okay”;

            };

pinmux.0x0243d040 = 0x00000454; # spi1_sck_pz3: spi1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d020 = 0x00000454; # spi1_miso_pz4: spi1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d058 = 0x00000454; # spi1_mosi_pz5: spi1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d010 = 0x00000458; # spi1_cs0_pz6: spi1, pull-up, tristate-enable, input-enable, lpdr-disable
pinmux.0x0243d050 = 0x00000458; # spi1_cs1_pz7: spi1, pull-up, tristate-enable, input-enable, lpdr-disable

3

Did you connected → SPI1_MOSI<- ->SPI3_MOSI, SPI1_MISO<- ->SPI3_MISO, SPI1_CLK<–>SPI3_CLK, SP1_CS0 <–> SPI3_CS0 and SPI1_CS1->SPI3_CS1. What’s you test command?

SPI1 has to be configured as Master and SPI3 has to be configured as slave in the dt and pinmux settings have to be updated.
SPI1 DT:
spi@3210000 {
status = “okay”;
compatible = “nvidia,tegra186-spi”;
spi@0 {
compatible = “spidev”;
reg = <0>;
spi-max-frequency = <65000000>;
controller-data {
nvidia,enable-hw-based-cs;
};
};
};

SPI3 DT
spi@3230000 {
status = “okay”;
compatible = “nvidia,tegra186-spi-slave”;
spi@0 {
compatible = “spidev”;
reg = <0>;
spi-max-frequency = <65000000>;
controller-data {
nvidia,enable-hw-based-cs;
};
};
};

PINMUX settings are listed below for SPI1 and SP13 for loopback. (Note: SPI1 and SP3 have an internal loopback connection for Xavier)

SPI_1 pinmux settings:
PADCTL_UART_SPI1_MISO_0 (0x0243d020) = 0x440;
PADCTL_UART_SPI1_MOSI_0 (0x0243d058) = 0x440;
PADCTL_UART_SPI1_SCK_0 (0x0243d040) = 0x440;
PADCTL_UART_SPI1_CS0_0 (0x0243d010) = 0x448;
PADCTL_UART_SPI1_CS1_0 (0x0243d050) = 0x448;

SPI_3 pinmux settings:
PADCTL_UART_SPI3_MISO_0 (0x0243d008) = 0x440;
PADCTL_UART_SPI3_MOSI_0 (0x0243d060) = 0x440;
PADCTL_UART_SPI3_SCK_0 (0x0243d048) = 0x444;
PADCTL_UART_SPI3_CS0_0 (0x0243d018) = 0x448;
PADCTL_UART_SPI3_CS1_0 (0x0243d028) = 0x448;

1 Like
4

Thanks for you response @ShaneCCC.

I made the changes you recommended with the DT and PINMUX settings, and I got to get the result I wanted using a SPI dongle MB85RS64V as a slave. I used an oscilloscope to verify the SCK, MOSI and MISO (based on the datasheet example) values and they matched my expectations. i.e. the hexadecimal output on the terminal was the same as the values displayed on the oscilloscope. I transmitted 9F using an hexadecimal array of length 6 (4 bytes was the minimum required length from the datasheet) and got back 04 7F 03 02.

I ran the test like this: ./spidev_test -D /dev/spidev*

FYI, the carrier board I’m using only has 1 SPI bus (SCK, MISO, MOSI, CS).

I’m wondering why NVIDIA has chosen to have one of the SPI busses on Xavier-Nx as master and the other as slave? Why can’t both SPIs be masters?

Also why are the pins connected like this: SPI1_MOSI<- ->SPI3_MOSI, SPI1_MISO<- ->SPI3_MISO, SPI1_CLK<–>SPI3_CLK, SP1_CS0 <–> SPI3_CS0 and SPI1_CS1->SPI3_CS1

Could you also please advise me why you chose the frequency 65000000Hz and how you came up with the values you used in the pinmux settings? None of the 3 available options for SPI pins (i.e. GPIO3_Px0x, unused_SPI1_xxxx, and SPI_xxxx) on the spread sheet match the values you used.

5

There’s no restrict for one as master other as slave.
Our suggest connect is for the loopback connect for test only.
You can check the TRM for detail of the REG setting.

7

Hi ShaneCCC

I followed you suggestion to modify DT and pinmux for xavier nx with R32.5.1.
But RX is not the same as TX.
You can see the command and response below.

p@p-desktop:/$ sudo ./spidev_test -v -s 65000000 -p 123 -D /dev/spidev0.0
spi mode: 0x0
bits per word: 8
max speed: 65000000 Hz (65000 KHz)
TX | 31 32 33 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  | 123
RX | FF FF FF __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  | ...
p@p-desktop:/$

Could you help me to solve this problem?

Thx
Yen

8

Do you short the MOSI/MISO for loopback test?

9

Hi ShaneCCC,

Do you mean connect these pins?
SPI1_MOSI<- ->SPI3_MOSI, SPI1_MISO<- ->SPI3_MISO, SPI1_CLK<–>SPI3_CLK, SP1_CS0 <–> SPI3_CS0 and SPI1_CS1->SPI3_CS1

If yes, I already have connected these pinss, but still can’t receive anything.

BTW, I used a logic analyzer to capture mosi, msio and clk signals.
I got some signals but can’t interpreted by the logic analyzer.
It seems like it has something wrong on the TX side.

Thx
Yen

10

Run below script.

sudo ./spidev_test -D /dev/spidev2.0 -s8000000 -g512 -b32 -H -p0 -n1 -r &
sleep 5
sudo ./spidev_test -D /dev/spidev0.0 -s8000000 -g512 -b32 -H -p0 -n1 -zzz -t

11

Hi ShaneCCC,

Thx.

Yen

12

sudo ./spidev_test -D /dev/spidev2.0 -s8000000 -g512 -b32 -H -p0 -n1 -r &
[1] 15654
zalend@zalend-desktop:~/test$ ./spidev_test: invalid option – ‘g’
Usage: ./spidev_test [-DsbdlHOLC3]
-D --device device to use (default /dev/spidev1.1)
-s --speed max speed (Hz)
-d --delay delay (usec)
-b --bpw bits per word
-l --loop loopback
-H --cpha clock phase
-O --cpol clock polarity
-L --lsb least significant bit first
-C --cs-high chip select active high
-3 --3wire SI/SO signals shared
-v --verbose Verbose (show tx buffer)
-p Send data (e.g. “1234\xde\xad”)
-N --no-cs no chip select
-R --ready slave pulls low to pause
-2 --dual dual transfer
-4 --quad quad transfer

Could you help me to solve this problem?Thanks

13

Download the binary from to try.

https://forums.developer.nvidia.com/uploads/short-url/orCHnP8AnFmCR2rxDDtmZOegMwi.txt