GPIO, SPI and PWM not working on Jetson Xavier NX

I have made a video to clearly show the problem that I am having see header problem - YouTube

I am using the Jetson on a Seed Stuios A206 carrier board which is their copy of the official dev kit carrier board as Nvidia is no longer manufacturing the official carrier board. I am running JetPack 5.01. I have also tried using Jetpack 4.6 but had the same problem.

In the video I said that I hadn’t got the UART to work but since then I have successfully used UART on pins 8 and 10 using /dev/ttyTHS0

Also as stated in the video I have successfully used the I2C bus on pins 3 and 5

hello Out_of_the_BOTS,

let’s start with GPIO issue,
are you able to toggle this pin through sysfs and see the high/low signal? i.e. GPIO11 / GPIO3_PQ.06 / gpio422,
here’re steps to generate gpio422 name from sysfs, create the node for controlling.
for example,
# echo 422 > /sys/class/gpio/export
# cd /sys/class/gpio/gpio422
# echo out > direction && echo [1/0] > value

There is not a gpio422 directory see below output

you’ll need to grant root permission to generate gpio422 name from sysfs

It did not change the reading on the pin. Is there a way to rule out a hardware problem with the A206 carrier board??

hello Out_of_the_BOTS,

sorry, I’ve given incorrect sample. (will also revise my previous comments)
please assign this to generate gpio422 name from sysfs, i.e. # echo 422 > /sys/class/gpio/export

That didn’t generate the gpio422

if I ls the directory this is what I get

hello Out_of_the_BOTS,

may I know which JetPack release version you’re using, is this native JetPack release image?
could you please share below information for reference, thanks
i.e. # cat /etc/nv_tegra_release, and $ dmesg | grep DTS

I used SDKmanger to flash Jetpack5.01 to the SSD

hello Out_of_the_BOTS,

there’s /sys/class/gpio/PO.01 created, please enter the node and try toggle the pin for confirmation.

I still didn’t get a change on the pin see following terminal output

I am testing GPIO422 aka GPIO11 aka header pin 31 in below picture

Screenshot from 2022-07-12 14-40-45

hello Out_of_the_BOTS,

there’s an issue to configure GPIO directly,
currently, if you would like to make changes dynamically, you may use devmem/reg_dump to update pinmux register , or update MB1 pinmux bct file.
for example,
pinmux.0x02430030 = 0x0000005a; # soc_gpio42_pq6: rsvd2, pull-up, tristate-enable, input-enable, io_high_voltage-disable, lpdr-disable

please set both bit-4 and bit-6 as 0 to configure this pin as output mode. after that, you should be able to control the pin through sysfs.
for example,
pinmux register: 0x02430030 / Default boot value: 0x5a
please update bit-4 and bit-6 to set required direction. whereas, Output: Bit 4 = 0 Bit 6=0, Input: Bit 4=1 Bit 6=1
please try below steps to make GPIO output working.

$ sudo devmem2 0x02430030 w 0x0a
$ echo [GPIO number] > /sys/class/gpio/export
$ cd /sys/class/gpio/PQ.06
$ echo out > direction
$ cat value # change value and check.

you’ll need to double check the gpio numbers. please see-also To check the GPIO number.
since I don’t have Xavier NX for double check, please examine the GPIO allocation range, you should check kernel init messages.
for example, this is the results by Orin AGX.

[    6.007898] gpiochip0: registered GPIOs 348 to 511 on tegra234-gpio
[    6.013957] gpiochip1: registered GPIOs 316 to 347 on tegra234-gpio-aon

this issue is fixed, you may expect next JetPack public release (l4t-r35.1) to include the fixes.

There doesn’t seem to be a GPIO allocation

because it’s naming is using tegra194-gpio and tegra194-gpio-aon.

GPIO 422 is within the GPIO list

I still haven’t been able to toggle a GPIO pin.

When will the update r35.1 be released?

I have also contacted Seed Studios about the issues incase it is a problem with the carrier board

hello Out_of_the_BOTS,

the gpio allocation range has changed for JP-5.0, the GPIO number (soc_gpio42_pq6) isn’t 422 as shown in NVIDIA Jetson Xavier NX GPIO Header Pinout - JetsonHacks.
please refer to below for GPIO calculation formula,

#define TEGRA194_MAIN_GPIO_PORT_Q 16

#define TEGRA194_MAIN_GPIO(port, offset)
((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset)

so, the gpio number of GPIO3_PQ.06 = ((16 * 8) + 6) + 335 = 469
you should try export the pin again, please check you’re able to make GPIO output working.

$ sudo devmem2 0x02430030 w 0x0a
$ echo 469 > /sys/class/gpio/export
$ cd /sys/class/gpio/PQ.06
$ echo out > direction
$ cat value # change value and check.


please refer to developer guide, To check a GPIO number,
please follow the GPIO debugfs for looking up the port and offset.
for example, 454 the GPIO number of PQ.06

$ sudo cat /sys/kernel/debug/gpio | grep PQ.06
 gpio-454 (PQ.06               )

I need to know which pin to check on the header. Which header pin responds to 469

the same pin you’re tested, pin-31 / GPIO11.

No change on the pin.