Why it’s CSI2/CSI3? Orin Nano should have two ports one is CSI0 and another port is CSI3.
It’s customized carrier camera board?
Hi
We have a customized carrier board with 4 2-Lane cameras and this setup:
video0 -> Port C -> CSI2
video1 -> Port D -> CSI3
video3 -> Port A -> CSI0
video4 -> Prot B -> CSI1
Here the customized DT:
tegra234-camera-ar0234-a00.txt (27.1 KB)
BR
Kris
Why all camera configure the lane_polarity?
We have all data lanes swizzled, that’s how they are configured with the lane_polarity paramater. Should that be done only once per PHY?
I reconfigured them:
serial_a: lane_polarity = 9
serial_b: lane_polarity = 9serial_c: lane_polarity = 15
serial_d: lane_polarity = 15
Still the same behaviour…
How about run 2 cameras CSI-A and CSI-C only.
That works fine. See table:
serial_a & serial_b → Fail
serial_a & serial_c → Successful
serial_a & serial_d → Successful
serial_b & serial_c → Successful
serial_b & serial_d → Successful
serial_c & serial_d → Fail
That’s tell your design have problem.
The problem could be the HW swizzled and lane_polarity cause resource busy to break. I would suggest to follow the design guide for your product.
Thanks
Hi Shane
Do I understand you correct? You mean that we shouldn’t use the option to swizzle the data lanes? We use this feature because we don’t want to swizzle them physically on the PCB.
Could it be that the problem is caused by the assigned /dev/videoX nodes?
video0 -> Port C -> CSI2
video1 -> Port D -> CSI3
video3 -> Port A -> CSI0
video4 -> Port B -> CSI1
Should that be done like that?
video0 -> Port A -> CSI0
video1 -> Port B -> CSI1
video3 -> Port C -> CSI2
video4 -> Port D -> CSI3
It doesn’t matter with the video node mapping.
The port A/B is a brick when you do the swizzle for A and B the same time would make data conflict cause problem.
Is it not possible to handle that at the device tree for a 4 camera 2-Lane configuration?
Hi Shane
I got it to run with PHY register manipulations via devmem2 tool. Now it’s clear that this error isn’t a hardware issue.
Steps to get them run concurrently:
- start v4l-ctrl for video2 on PHY_0 CIL_A
v4l2-ctl -d /dev/video2 --set-ctrl bypass_mode=0 --stream-mmap --set-fmt-video=width=1920,height=1200,pixelformat=BA10 --verbose
- start v4l-ctrl for video3 on PHY_0 CIL_B
v4l2-ctl -d /dev/video3 --set-ctrl bypass_mode=0 --stream-mmap --set-fmt-video=width=1920,height=1200,pixelformat=BA10 --verbose
- set the PHY_0 and CIL_B register to correct values
devmem2 0x15a11c08 w 0x70D
devmem2 0x15a11c10 h 0x202devmem2 0x15a11de0 w 0x2
devmem2 0x15a11d8e h 0x70
devmem2 0x15a11de4 h 0x7411
devmem2 0x15a11de8 w 0x4B970505
video3 starts streaming…
Have you any suggestions why the PHY registers are not correct set? Which kernel device driver is responsible for the PHY configuration?
BR
Kris
- What’s your HW swizzle?
- Need program both of those REG? Cold you read it after start the v4l2-ctl to confirm which REG is the key point.
We changed the lane polarity for all 8 data lanes. On the Orin Nano CSI_0_D1_N/P and CSI1_D0_N/P are swizzled.
lane_polarity for PHY0 0x9
lane_polarity for PHY1 0xF
No, it’s enough to manipulate the register posted above.
Here is a list of reading the registers at different stages:
REG Values: video2 started, video3 not
root@tegra-ubuntu:~# devmem2 0x15a11c08 w
Value at address 0x15A11C08 (0xffffb4f97c08): 0x60Droot@tegra-ubuntu:~# devmem2 0x15a11c10 h
Value at address 0x15A11C10 (0xffffa77cbc10): 0x2root@tegra-ubuntu:~# devmem2 0x15a11de0 w
Value at address 0x15A11DE0 (0xffff916aede0): 0x0root@tegra-ubuntu:~# devmem2 0x15a11d8e h
Value at address 0x15A11D8E (0xffff90c7ed8e): 0x7root@tegra-ubuntu:~# devmem2 0x15a11de8 w
Value at address 0x15A11DE8 (0xffff91f51de8): 0x4B960000
REG Values: video2 & video3 started
root@tegra-ubuntu:~# devmem2 0x15a11c08 w
Value at address 0x15A11C08 (0xffff8e886c08): 0x60Droot@tegra-ubuntu:~# devmem2 0x15a11c10 h
Value at address 0x15A11C10 (0xffffa6c60c10): 0x2root@tegra-ubuntu:~# devmem2 0x15a11de0 w
Value at address 0x15A11DE0 (0xffff913e4de0): 0x0root@tegra-ubuntu:~# devmem2 0x15a11d8e h
Value at address 0x15A11D8E (0xffffa3d28d8e): 0x7root@tegra-ubuntu:~# devmem2 0x15a11de8 w
Value at address 0x15A11DE8 (0xffff9ae51de8): 0x4B960000
REG Values: video2 startet, set REG values and than video3 started
root@tegra-ubuntu:~# devmem2 0x15a11c08 w
Value at address 0x15A11C08 (0xffffaf6f6c08): 0x70Droot@tegra-ubuntu:~# devmem2 0x15a11c10 h
Value at address 0x15A11C10 (0xffff96555c10): 0x2root@tegra-ubuntu:~# devmem2 0x15a11de0 w
Value at address 0x15A11DE0 (0xffff8b88ade0): 0x0root@tegra-ubuntu:~# devmem2 0x15a11d8e h
Value at address 0x15A11D8E (0xffffaf99dd8e): 0x74root@tegra-ubuntu:~# devmem2 0x15a11de8 w
Value at address 0x15A11DE8 (0xffff886d5de8): 0x4B970505
The last list is interesting. The bold values are overwritten when video3 starts.
Does video3 working if write 0x15a11de0 only?
devmem2 0x15a11de0 w 0x2
No. I did try some combinations but at every combination video3 did start streaming when all the registers where written.
Is the csi5_fops.c kernel driver file responsible for the MIPI PHY register access?
If your 8 lanes are swizzle the lane_polarity show set the 0xF and the REG 0x15a11de0 should be 0x3.
Hi Shane
video3 is connected to PHY0 CIL_B. This data lanes are swizzled on Orin Nano Device.
Than the lane polarity should be set to 0x2 instead of 0x3. If set to 0x3 video3 doesn’t start streaming.
So base on this Figure 10-1 which CSI* are swizzled for your design?
Got it to run with the following Device Tree configuration.
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/ {
tegra-capture-vi {
num-channels = <4>;
ports {
#address-cells = <1>;
#size-cells = <0>;
vi_port0: port@0 {
reg = <0>;
liar0234_vi_in0: endpoint {
port-index = <0>;
bus-width = <2>;
remote-endpoint = <&liar0234_csi_out0>;
};
};
vi_port1: port@1 {
reg = <1>;
liar0234_vi_in1: endpoint {
port-index = <1>;
bus-width = <2>;
remote-endpoint = <&liar0234_csi_out1>;
};
};
vi_port2: port@2 {
reg = <2>;
liar0234_vi_in2: endpoint {
port-index = <2>;
bus-width = <2>;
remote-endpoint = <&liar0234_csi_out2>;
};
};
vi_port3: port@3 {
reg = <3>;
liar0234_vi_in3: endpoint {
port-index = <3>;
bus-width = <2>;
remote-endpoint = <&liar0234_csi_out3>;
};
};
};
};
host1x@13e00000 {
nvcsi@15a00000 {
num-channels = <4>;
#address-cells = <1>;
#size-cells = <0>;
csi_chan0: channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0234_csi_in0: endpoint@0 {
port-index = <0>;
bus-width = <2>;
remote-endpoint = <&liar0234_ar0234_out0>;
};
};
port@1 {
reg = <1>;
liar0234_csi_out0: endpoint@1 {
remote-endpoint = <&liar0234_vi_in0>;
};
};
};
};
csi_chan1: channel@1 {
reg = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0234_csi_in1: endpoint@0 {
port-index = <1>;
bus-width = <2>;
remote-endpoint = <&liar0234_ar0234_out1>;
};
};
port@1 {
reg = <1>;
liar0234_csi_out1: endpoint@1 {
remote-endpoint = <&liar0234_vi_in1>;
};
};
};
};
csi_chan2: channel@2 {
reg = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0234_csi_in2: endpoint@0 {
port-index = <2>;
bus-width = <2>;
remote-endpoint = <&liar0234_ar0234_out2>;
};
};
port@1 {
reg = <1>;
liar0234_csi_out2: endpoint@1 {
remote-endpoint = <&liar0234_vi_in2>;
};
};
};
};
csi_chan3: channel@3 {
reg = <3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0234_csi_in3: endpoint@0 {
port-index = <3>;
bus-width = <2>;
remote-endpoint = <&liar0234_ar0234_out3>;
};
};
port@1 {
reg = <1>;
liar0234_csi_out3: endpoint@1 {
remote-endpoint = <&liar0234_vi_in3>;
};
};
};
};
};
};
i2c@3180000 {
tca9546@70 {
i2c@0 {
ar0234_cam1: ar0234_b@18 {
compatible = "nvidia,ar0234";
/* I2C device address */
reg = <0x18>;
/* Input clock name */
mclk = "extperiph1";
/* V4L2 device node location ATTENTION has no effect! Devnotes are given by invoke sequence */
devnode = "video0";
/* Physical dimensions of sensor */
physical_w = "9.995";
physical_h = "5.595";
sensor_model ="ar0234";
use_decibel_gain = "true";
/* enable CID_SENSOR_MODE_ID for sensor modes selection */
use_sensor_mode_id = "true";
/* NOTE specifie the sensor id, valid values 0-3. used at ar0234 driver to access correct struct */
ar0234_sensor_id = "1";
mode0 { /*fix 10 FPS*/
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_c";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "130"; /* k.w modified NOTE THS-Settle measured at MIPI clock signal, see Understanding_and_Performing_MIPI.pdf */
lane_polarity = "15";
csi_pixel_bit_depth = "10";
mode_type = "bayer";
pixel_phase = "grbg";
active_w = "1920";
active_h = "1200";
readout_orientation = "0";
line_length = "612"; // "2448"; /* k.w modified NOTE value from registar wizard 0x300C */
inherent_gain = "1";
pix_clk_hz = "300000000"; /* k.w modified NOTE min val 100000000 */
min_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
max_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
gain_factor = "100";
min_gain_val = "170";
max_gain_val = "1600";
step_gain_val = "2";
default_gain = "200";
framerate_factor = "1000000";
min_framerate = "10000000";
max_framerate = "10000000";
step_framerate = "1";
default_framerate= "10000000";
exposure_factor = "1000000";
min_exp_time = "20"; /* 20 us */
max_exp_time = "33333"; /* 33333 us */
step_exp_time = "2"; /* k.w modified NOTE only even values are allowed */
default_exp_time = "8330"; /* 8330 us */
embedded_metadata_height = "0";
};
mode1 { /* max 30 FPS*/
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_c";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "130"; /* k.w modified NOTE THS-Settle measured at MIPI clock signal, see Understanding_and_Performing_MIPI.pdf */
lane_polarity = "15";
csi_pixel_bit_depth = "10";
mode_type = "bayer";
pixel_phase = "grbg";
active_w = "1920";
active_h = "1200";
readout_orientation = "0";
line_length = "612"; // "2448"; /* k.w modified NOTE value from registar wizard 0x300C */
inherent_gain = "1";
pix_clk_hz = "300000000"; /* k.w modified NOTE min val 100000000 */
min_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
max_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
gain_factor = "100";
min_gain_val = "170";
max_gain_val = "1600";
step_gain_val = "2";
default_gain = "200";
framerate_factor = "1000000";
min_framerate = "10000000";
max_framerate = "30000000";
step_framerate = "1";
default_framerate= "10000000";
exposure_factor = "1000000";
min_exp_time = "20"; /* 20 us */
max_exp_time = "33333"; /* 33333 us */
step_exp_time = "2"; /* k.w modified NOTE only even values are allowed */
default_exp_time = "8330"; /* 8330 us */
embedded_metadata_height = "0";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0234_ar0234_out2: endpoint {
port-index = <2>;
bus-width = <2>;
remote-endpoint = <&liar0234_csi_in2>;
};
};
};
};
};
i2c@1 {
ar0234_cam0: ar0234_a@18 {
compatible = "nvidia,ar0234";
/* I2C device address */
reg = <0x18>;
/* Input clock name */
mclk = "extperiph1";
/* V4L2 device node location ATTENTION has no effect! Devnotes are given by invoke sequence */
devnode = "video1";
/* Physical dimensions of sensor */
physical_w = "9.995";
physical_h = "5.595";
sensor_model ="ar0234";
use_decibel_gain = "true";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
//avdd-reg = "vana";
//iovdd-reg = "vif";
//dvdd-reg = "vdig";
/* Defines number of frames to be dropped by driver internally after applying
sensor crop settings. Some sensors send corrupt frames after applying
crop co-ordinates */
//post_crop_frame_drop = "0";*/
/* if true, delay gain setting by one frame to be in sync with exposure */
//delayed_gain = "true";
/* enable CID_SENSOR_MODE_ID for sensor modes selection */
use_sensor_mode_id = "true";
/* NOTE specifie the sensor id, valid values 0-3. used at ar0234 driver to access correct struct */
ar0234_sensor_id = "0";
/**
* ==== Modes ====
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* == Signal properties ==
*
* phy_mode = "";
* PHY mode used by the MIPI lanes for this device
*
* tegra_sinterface = "";
* CSI Serial interface connected to tegra
* Incase of virtual HW devices, use virtual
* For SW emulated devices, use host
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
* NOTE evalueted with measurement of pixel-Clock and adjust value until it is correct set to 250MHz
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* lane_polarity
* Based on the camera connector pin.
* CSIx_D0 | CSIx_D1 | CSI(X+1)_D0 | CSI(X+1)CSIx_D1
* LSB | BIT1 | BIT2 | MSB
* if there is a polarity swap on any lane, the bit corrsponding
* to the lane should be set
* e.g. polarity swap on CSIx_D0 only -> lane_polarity = "1"; 0001
* e.g. polarity swap on CSIx_D1 and CSI(X+1)_D0 -> lane_polarity = "6"; 0110
*
* == Image format Properties ==
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* line_length = "";
* Pixel line length (width) for sensor mode.
*
* == Source Control Settings ==
*
* Gain factor used to convert fixed point integer to float
* Gain range [min_gain/gain_factor, max_gain/gain_factor]
* Gain step [step_gain/gain_factor is the smallest step that can be configured]
* Default gain [Default gain to be initialized for the control.
* use min_gain_val as default for optimal results]
* Framerate factor used to convert fixed point integer to float
* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
* Default Framerate [Default framerate to be initialized for the control.
* use max_framerate to get required performance]
* Exposure factor used to convert fixed point integer to float
* For convenience use 1 sec = 1000000us as conversion factor
* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
* Default Exposure Time [Default exposure to be initialized for the control.
* Set default exposure based on the default_framerate for optimal exposure settings]
*
* gain_factor = ""; (integer factor used for floating to fixed point conversion)
* min_gain_val = ""; (ceil to integer)
* max_gain_val = ""; (ceil to integer)
* step_gain_val = ""; (ceil to integer)
* default_gain = ""; (ceil to integer)
* Gain limits for mode
*
* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* step_exp_time = ""; (ceil to integer)
* default_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (sec)
*
* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
* min_framerate = ""; (ceil to integer)
* max_framerate = ""; (ceil to integer)
* step_framerate = ""; (ceil to integer)
* default_framerate = ""; (ceil to integer)
* Framerate limits for mode (fps)
*
* embedded_metadata_height = "";
* Sensor embedded metadata height in units of rows.
* If sensor does not support embedded metadata value should be 0.
*/
mode0 { /*fix 10FPS*/
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_d";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "130"; /* k.w modified NOTE THS-Settle measured at MIPI clock signal, see Understanding_and_Performing_MIPI.pdf */
lane_polarity = "15";
csi_pixel_bit_depth = "10";
mode_type = "bayer";
pixel_phase = "grbg";
active_w = "1920";
active_h = "1200";
readout_orientation = "0";
line_length = "612"; // "2448"; /* k.w modified NOTE value from registar wizard 0x300C */
inherent_gain = "1";
pix_clk_hz = "300000000"; /* k.w modified NOTE min val 100000000 */
min_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
max_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
gain_factor = "100";
min_gain_val = "170";
max_gain_val = "1600";
step_gain_val = "2";
default_gain = "200";
framerate_factor = "1000000";
min_framerate = "10000000";
max_framerate = "10000000";
step_framerate = "1";
default_framerate= "10000000";
exposure_factor = "1000000";
min_exp_time = "20"; /* 20 us */
max_exp_time = "33333"; /* 33333 us */
step_exp_time = "2"; /* k.w modified NOTE only even values are allowed */
default_exp_time = "8330"; /* 8330 us */
embedded_metadata_height = "0";
};
mode1 { /* max 30 FPS*/
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_d";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "130"; /* k.w modified NOTE THS-Settle measured at MIPI clock signal, see Understanding_and_Performing_MIPI.pdf */
lane_polarity = "15";
csi_pixel_bit_depth = "10";
mode_type = "bayer";
pixel_phase = "grbg";
active_w = "1920";
active_h = "1200";
readout_orientation = "0";
line_length = "612"; // "2448"; /* k.w modified NOTE value from registar wizard 0x300C */
inherent_gain = "1";
pix_clk_hz = "300000000"; /* k.w modified NOTE min val 100000000 */
min_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
max_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
gain_factor = "100";
min_gain_val = "170";
max_gain_val = "1600";
step_gain_val = "2";
default_gain = "200";
framerate_factor = "1000000";
min_framerate = "10000000";
max_framerate = "30000000";
step_framerate = "1";
default_framerate= "10000000";
exposure_factor = "1000000";
min_exp_time = "20"; /* 20 us */
max_exp_time = "33333"; /* 33333 us */
step_exp_time = "2"; /* k.w modified NOTE only even values are allowed */
default_exp_time = "8330"; /* 8330 us */
embedded_metadata_height = "0";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0234_ar0234_out3: endpoint {
port-index = <3>;
bus-width = <2>;
remote-endpoint = <&liar0234_csi_in3>;
};
};
};
};
};
i2c@2 {
ar0234_cam2: ar0234_c@18 {
compatible = "nvidia,ar0234";
/* I2C device address */
reg = <0x18>;
/* Input clock name */
mclk = "extperiph1";
/* V4L2 device node location */
devnode = "video2";
/* Physical dimensions of sensor */
physical_w = "9.995";
physical_h = "5.595";
sensor_model ="ar0234";
use_decibel_gain = "true";
/* enable CID_SENSOR_MODE_ID for sensor modes selection */
use_sensor_mode_id = "true";
/* NOTE specifie the sensor id, valid values 0-3. used at ar0234 driver to access correct struct */
ar0234_sensor_id = "2";
mode0 { /*fix 10 FPS*/
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_a";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "130"; /* k.w modified NOTE THS-Settle measured at MIPI clock signal, see Understanding_and_Performing_MIPI.pdf */
lane_polarity = "9";
csi_pixel_bit_depth = "10";
mode_type = "bayer";
pixel_phase = "grbg";
active_w = "1920";
active_h = "1200";
readout_orientation = "0";
line_length = "612"; // "2448"; /* k.w modified NOTE value from registar wizard 0x300C */
inherent_gain = "1";
pix_clk_hz = "300000000"; /* k.w modified NOTE min val 100000000 */
min_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
max_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
gain_factor = "100";
min_gain_val = "170";
max_gain_val = "1600";
step_gain_val = "2";
default_gain = "200";
framerate_factor = "1000000";
min_framerate = "10000000";
max_framerate = "10000000";
step_framerate = "1";
default_framerate= "10000000";
exposure_factor = "1000000";
min_exp_time = "20"; /* 20 us */
max_exp_time = "33333"; /* 33333 us */
step_exp_time = "2"; /* k.w modified NOTE only even values are allowed */
default_exp_time = "8330"; /* 8330 us */
embedded_metadata_height = "0";
};
mode1 { /*max 30 FPS*/
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_a";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "130"; /* k.w modified NOTE THS-Settle measured at MIPI clock signal, see Understanding_and_Performing_MIPI.pdf */
lane_polarity = "9";
csi_pixel_bit_depth = "10";
mode_type = "bayer";
pixel_phase = "grbg";
active_w = "1920";
active_h = "1200";
readout_orientation = "0";
line_length = "612"; // "2448"; /* k.w modified NOTE value from registar wizard 0x300C */
inherent_gain = "1";
pix_clk_hz = "300000000"; /* k.w modified NOTE min val 100000000 */
min_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
max_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
gain_factor = "100";
min_gain_val = "170";
max_gain_val = "1600";
step_gain_val = "2";
default_gain = "200";
framerate_factor = "1000000";
min_framerate = "10000000";
max_framerate = "30000000";
step_framerate = "1";
default_framerate= "10000000";
exposure_factor = "1000000";
min_exp_time = "20"; /* 20 us */
max_exp_time = "33333"; /* 33333 us */
step_exp_time = "2"; /* k.w modified NOTE only even values are allowed */
default_exp_time = "8330"; /* 8330 us */
embedded_metadata_height = "0";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0234_ar0234_out0: endpoint {
port-index = <0>;
bus-width = <2>;
remote-endpoint = <&liar0234_csi_in0>;
};
};
};
};
};
i2c@3 {
ar0234_cam3: ar0234_d@18 {
compatible = "nvidia,ar0234";
/* I2C device address */
reg = <0x18>;
/* Input clock name */
mclk = "extperiph1";
/* V4L2 device node location */
devnode = "video3";
/* Physical dimensions of sensor */
physical_w = "9.995";
physical_h = "5.595";
sensor_model ="ar0234";
use_decibel_gain = "true";
/* enable CID_SENSOR_MODE_ID for sensor modes selection */
use_sensor_mode_id = "true";
/* NOTE specifie the sensor id, valid values 0-3. used at ar0234 driver to access correct struct */
ar0234_sensor_id = "3";
mode0 { /*fix 10 FPS*/
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_b";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "130"; /* k.w modified NOTE THS-Settle measured at MIPI clock signal, see Understanding_and_Performing_MIPI.pdf */
lane_polarity = "9";
csi_pixel_bit_depth = "10";
mode_type = "bayer";
pixel_phase = "grbg";
active_w = "1920";
active_h = "1200";
readout_orientation = "0";
line_length = "612"; // "2448"; /* k.w modified NOTE value from registar wizard 0x300C */
inherent_gain = "1";
pix_clk_hz = "300000000"; /* k.w modified NOTE min val 100000000 */
min_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
max_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
gain_factor = "100";
min_gain_val = "170";
max_gain_val = "1600";
step_gain_val = "2";
default_gain = "200";
framerate_factor = "1000000";
min_framerate = "10000000";
max_framerate = "10000000";
step_framerate = "1";
default_framerate= "10000000";
exposure_factor = "1000000";
min_exp_time = "20"; /* 20 us */
max_exp_time = "33333"; /* 33333 us */
step_exp_time = "2"; /* k.w modified NOTE only even values are allowed */
default_exp_time = "8330"; /* 8330 us */
embedded_metadata_height = "0";
};
mode1 { /* max 30 FPS*/
mclk_khz = "24000";
num_lanes = "2";
tegra_sinterface = "serial_b";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "130"; /* k.w modified NOTE THS-Settle measured at MIPI clock signal, see Understanding_and_Performing_MIPI.pdf */
lane_polarity = "9";
csi_pixel_bit_depth = "10";
mode_type = "bayer";
pixel_phase = "grbg";
active_w = "1920";
active_h = "1200";
readout_orientation = "0";
line_length = "612"; // "2448"; /* k.w modified NOTE value from registar wizard 0x300C */
inherent_gain = "1";
pix_clk_hz = "300000000"; /* k.w modified NOTE min val 100000000 */
min_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
max_hdr_ratio = "1"; /* k.w modified NOTE only used for HDR sensor */
gain_factor = "100";
min_gain_val = "170";
max_gain_val = "1600";
step_gain_val = "2";
default_gain = "200";
framerate_factor = "1000000";
min_framerate = "10000000";
max_framerate = "30000000";
step_framerate = "1";
default_framerate= "10000000";
exposure_factor = "1000000";
min_exp_time = "20"; /* 20 us */
max_exp_time = "33333"; /* 33333 us */
step_exp_time = "2"; /* k.w modified NOTE only even values are allowed */
default_exp_time = "8330"; /* 8330 us */
embedded_metadata_height = "0";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
liar0234_ar0234_out1: endpoint {
port-index = <1>;
bus-width = <2>;
remote-endpoint = <&liar0234_csi_in1>;
};
};
};
};
};
};
};
};
/ {
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
* Set this to the highest pix_clk_hz out of all available modes in kHz. NOTE k.w modified
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <8>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <750000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. "rear" or "front".
* NOTE k.w Four camera setup see https://forums.developer.nvidia.com/t/xavier-multiple-camera-connection-probelms/69753/19
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*
* ISP Configs available and testet:
* - liar0234 (Leopardimage)
* - A6V26
* - RPB194
* - RBPCV3
* - RBP234
* The best ISP configuration mode is RBP234 for Monochrome and RGB sensors
*/
modules {
module0 {
badge = "ar0234_bottomleft_liar0234";
position = "bottomleft";
orientation = "0"; /* k.w modified */
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ar0234 30-0018";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@0/ar0234_b@18";
};
};
module1 {
badge = "ar0234_topleft_liar0234";
position = "topleft";
orientation = "0"; /* k.w modified */
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ar0234 31-0018";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@1/ar0234_a@18";
};
};
module2 {
badge = "ar0234_bottomright_liar0234";
position = "bottomright";
orientation = "0"; /* k.w modified */
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ar0234 32-0018";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@2/ar0234_c@18";
};
};
module3 {
badge = "ar0234_topright_liar0234";
position = "topright";
orientation = "0"; /* k.w modified */
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Driver v4l2 device name */
devname = "ar0234 33-0018";
/* Declare the device-tree hierarchy to driver instance */
proc-device-tree = "/proc/device-tree/i2c@3180000/tca9546@70/i2c@3/ar0234_d@18";
};
};
};
};
};
Thank you very much for guiding me throw this debugging process…
This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.