hello 1508723374,
it’s LP sequence error detected on data lane. this usually an issue on sensor side.
note,
there’s sequence, LP11->LP01->LP00->LP11. when moving from LP to HS. the settle time determine how many cscil clock cycles to wait after LP00.
hence…
you may configure cil_settletime, it’s the property to tune the transition time from LP to HS mode.
please see-also developer guide for more details of cil_settletime property.