How to config GPIO clock freq?

We use 4 GPU GPIO to download the FPGA firmware on customer carried board.
About the FPGA download , we use the same mode with a TX2 customer carried board.
Download time:(the same Firmware file)
1) TX2 : about 120 seconds;
2) ORIN NX : about 370 seconds;
How to reduce the download time on ORIN NX;


Hi wangqunpj,

Is there any serial console log during downloading the FPGA firmware for both TX2 and Orin NX?

How do you use GPIO to download the FPGA firmware?

Could you reproduce the same behavior on the devkit?

TX2_serial_log.txt (27.1 KB)
ORIN_NX.txt (87.2 KB)

we use GPU GPIO to Timing Simulation FPGA DOWNLOAD

Sorry, I don’t see any message about downloading FPGA firmware. There’s only the boot up logs. Please run your application with timestamp to download FPGA firmware.

May I know what is “GPU GPIO”?
What is the interface you used to communicate with FPGA?

This four GPIO are used to load FPGA firmware.

How did you configure PIN128 (GPIO05) to as serial_out? Isn’t it configured as GPIO instead of serial?

Please provide the serial console log to check if there’s any error or delay during downloading.


  1. 我们用ORIN NX来加载XILINX FPGA的固件(也就是.bit),也就是Slave Serial mode,上面有图示给出了加载的时序图;
  3. 例如: GPIO05是数据线,用于传输FPGA固件的每一位bit,根据时序要求,每一个时钟上升沿,就传输1个bit.这个GPIO05只做普通GPIO使用;
  4. 例如: GPIO04用于产生时钟,即这个GPIO先拉低,隔一个固定时间,再拉高保持一个固定时间。 如此循环即产生了需要的时钟。.这个GPIO04只做普通GPIO使用;
    我们已经通过这种方式在ORIN NX自研载板上成功加载了FPGA,使用同样的加载方式在TX2的自研载板上也成功加载了FPGA,但我们发现,ORIN NX用时会比TX2多200多秒,我们不确定是什么原因导致了ORINNX加载时间变长。


for example

when runing code above on ORIN NX,we can find the square wave about 110khz through the oscilloscope.

How to increase GPIO frequency,then get a higher square wave frequency?

請問是否有透過示波器比較過data/clock rate在TX2及OrinNX的差異?

Have you tried if TX2 generate the same 110kHz with this approach?

Let me check with our internal.

the value we got from TX2 is about 400KHz
below is we search in forum

So, The difference between TX2 and OrinNX seems caused from the clock rate of GPIO.

The clock rate for GPIO could be configured with the following node.

#cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/rate

It seems been configured as the same as max_rate at 204MHz for Orin NX already.

please see this pdf:
Orin-TRM_DP10508002v1.1p.pdf – Bit Banging Use Cases

for TX2:
1)cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/rate
2) cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/max_rate
1)cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/rate
2) cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/max_rate
3) cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/dvfs
vdd_core 204000000 606512
vdd_core 408000000 692658

the questions:

  1. the ORIN NX default rate is 204M,the TX2 is default rate is 115M
    but, the TX2 toggle speed is 0.33M, the ORIN NX is 0.11M
  2. How to modify the rate of the ORIN NX

Could you try to modify the following in BPMP-DTB and check the max_rate for axi_cbb again?

		clock@axi_cbb {
			clk-id = <0x8>;
-			max-rate-maxn = <0x0 0xc28cb00>;
+			max-rate-maxn = <0x0 0x18519600>;

The code provided in which DTS/DTSI file?

Please share your flash log and I will instruct you for which dtb in use for bpmp.

Has been modified the max_rate,but it is 405000000,not 408000000, why?

I don’t have idea about why you show 405MHz.
Could you write axi_cbb/rate to higher value with echo?
and please check if the FPGA download time get improved.

the FPGA download time has got improved, the time is from 370s to 250s

  1. TX2 default is 115M, but the download firmware only 120s
    ORIN NX is 204M, higher than TX2,why need the longer time than TX2?
  2. TX2 can be set to 409M,download firmware only 50s
    ORIN NX set to 408M, but download firmware need 250s

please help to analyze ORIN NX ,how to improve the download time?
(at the same time , analyze the difference between ORIN NX and TX2)

Sorry, it’s hard for us to analyze the difference between Orin NX and TX2. They are from different series and also the Jetpack release. We don’t have the Xilinx FPGA and even your custom board.
What we could do now is providing the method to increase GPIO clock because you are using GPIO for FPGA firmware download.

Do you have any reproduce steps on the devkit and we could do further check?