We use 4 GPU GPIO to download the FPGA firmware on customer carried board.
About the FPGA download , we use the same mode with a TX2 customer carried board.
Download time:(the same Firmware file)
1） TX2 : about 120 seconds;
2） ORIN NX : about 370 seconds;
How to reduce the download time on ORIN NX;
Thanks
Hi wangqunpj,
Is there any serial console log during downloading the FPGA firmware for both TX2 and Orin NX?
How do you use GPIO to download the FPGA firmware?
Could you reproduce the same behavior on the devkit?
TX2_serial_log.txt (27.1 KB)
ORIN_NX.txt (87.2 KB)
Sorry, I don’t see any message about downloading FPGA firmware. There’s only the boot up logs. Please run your application with timestamp to download FPGA firmware.
May I know what is “GPU GPIO”?
What is the interface you used to communicate with FPGA?
How did you configure PIN128 (GPIO05) to as serial_out? Isn’t it configured as GPIO instead of serial?
Please provide the serial console log to check if there’s any error or delay during downloading.
我来用中文描述一下问题
因为我们是用GPIO加载的，所以没有系统相关的log文件打印输出
for example
while(1)
{
SET_GPIO04(0);
SET_GPIO04(1);
}
when runing code above on ORIN NX,we can find the square wave about 110khz through the oscilloscope.
question:
How to increase GPIO frequency,then get a higher square wave frequency?
若無相關log會較難debug問題點
請問是否有透過示波器比較過data/clock rate在TX2及OrinNX的差異?
Have you tried if TX2 generate the same 110kHz with this approach?
Let me check with our internal.
So, The difference between TX2 and OrinNX seems caused from the clock rate of GPIO.
The clock rate for GPIO could be configured with the following node.
#cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/rate
It seems been configured as the same as max_rate at 204MHz for Orin NX already.
for TX2:
1)cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/rate
115200000
2) cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/max_rate
409600000
for ORIN NX
1)cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/rate
204000000
2) cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/max_rate
204000000
3) cat /sys/kernel/debug/bpmp/debug/clk/axi_cbb/dvfs
vdd_core 204000000 606512
vdd_core 408000000 692658
the questions:
Could you try to modify the following in BPMP-DTB and check the max_rate for axi_cbb again?
clock@axi_cbb {
clk-id = <0x8>;
- max-rate-maxn = <0x0 0xc28cb00>;
+ max-rate-maxn = <0x0 0x18519600>;
};
The code provided in which DTS/DTSI file?
Please share your flash log and I will instruct you for which dtb in use for bpmp.
Has been modified the max_rate,but it is 405000000,not 408000000, why?
I don’t have idea about why you show 405MHz.
Could you write axi_cbb/rate to higher value with echo?
and please check if the FPGA download time get improved.
the FPGA download time has got improved, the time is from 370s to 250s
qestion:
please help to analyze ORIN NX ,how to improve the download time?
(at the same time , analyze the difference between ORIN NX and TX2)
Sorry, it’s hard for us to analyze the difference between Orin NX and TX2. They are from different series and also the Jetpack release. We don’t have the Xilinx FPGA and even your custom board.
What we could do now is providing the method to increase GPIO clock because you are using GPIO for FPGA firmware download.
Do you have any reproduce steps on the devkit and we could do further check?