How to decrease the delay between spi transfer?

Robotics & Edge Computing Jetson & Embedded Systems Jetson Nano
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1

Hi all,
I test the spi speed and found the gap between transfer is abnormal.
had patched
Bug200580239
Bug3053593

patch file in the How to decrease the delay between spi transfer and CS action? - #10 by zyxhuo.

used dts of spidev0 as below:
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test transfer tx and rx with one byte four times.
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and the gap as below, could be ~1.5ms

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test with SPI_IOC_MESSAGE(2),
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and the gap still be ~350us,
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is anyone who can help me? where is my wrong?

tks

3

@kayccc
could you help?
tks

4

Have internal developer to check. May take time to check it.

Thanks

5

@ShaneCCC
k, tks very much.

6

@ShaneCCC
Please Could you check this issue?

9

There is no update from you for a period, assuming this is not an issue any more.
Hence we are closing this topic. If need further support, please open a new one.
Thanks

May I know the version for your test?
Could you try the latest release r32.5.x