Hi all,
I test the spi speed and found the gap between transfer is abnormal.
had patched
Bug200580239
Bug3053593
patch file in the How to decrease the delay between spi transfer and CS action? - #10 by zyxhuo.
used dts of spidev0 as below:
test transfer tx and rx with one byte four times.
and the gap as below, could be ~1.5ms
test with SPI_IOC_MESSAGE(2),
and the gap still be ~350us,
is anyone who can help me? where is my wrong?
tks