hello sclsdhlr,
please access Xavier Series (SoC) Technical Reference Manual via Jetson Download Center,
please refer to [9.5.4 PinMux Registers]-> [AO PAD Control Registers] session.
you should configure below registers, modify bit [1:0] to 0x1 will select UARTG function.
PADCTL_AO_SPI2_MOSI_0 | offset: 0x28
PADCTL_AO_SPI2_CS0_0 | offset: 0x38
PADCTL_AO_SPI2_SCK_0 | offset: 0x48
PADCTL_AO_SPI2_MISO_0 | offset: 0x50
you may working with debug tools, such as dev2mem to write register directly,
Or, you may check Jetson AGX Xavier MB1 Platform Configuration chapter for the steps to update the pinmux config.
thanks