NX change console to other uart

Instead of default ttyTCU0.
Is there any way to change console-port to other uart port ?

Since I’ve tried to modify tegra194-p3668-common.dtsi and cboot source code to switch/disable console uart,
it makes no affect that console still comes out from ttyTHS0 /ttyTCU0 with tegra-combined-uart mechanism.

cboot:

tegra194-p3668-common.dtsi
chosen {
bootargs =“console=ttyTHS1,115200”;
board-has-eeprom;
nvidia,tegra-joint_xpu_rail;
};

hello Wiser.Kuo,

Jetson Xavier NX brings three UARTs out to the main connector; you may access NX Product Design Guide, and check [Table 10-7] for pin descriptions.

you may search serial ports which enabling by ttyUSB* for sending serial data,
checking $ ls -la /dev/ttyUSB* on your host Ubuntu machine, and using picocom or minicom utility to connect for uart logs, the baudrate settings is 115200/8n1 by default.
thanks

Hi Jerry:
For table 10-7 , What does it mean for “debug uart” at UART3 pin 236 ,238 ?
Since the terminal login messages are showed from UART1 pin 203 205 207 209 on our re-designed carrier board.
as below: (connect to usb-serial cable with host pc)
qbic-desktop login:
Ubuntu 18.04.4 LTS qbic-desktop ttyTHS0

but in table 10-7 , this port is general uart UART1 .

What’s the related uart id in dts with these UARTs?

hello Wiser.Kuo,

you may refer to kernel initial messages, check all mounted serial ports,
for example,
$ dmesg | grep THS

you may access L4T sources packages for public release sources, you may check device tree settings for the mappings.
for example,
$L4T_Sources/r32.4.3/Linux_for_Tegra/source/public/hardware/nvidia/soc/t19x/kernel-dts/tegra194-soc/tegra194-soc-uart.dtsi

please also check similar discussion thread, Topic 125337 for reference.
thanks

Hi Jerry:

Now the bsp i use is L4T r32.4.3
The default uart related settings in tegra194-p3668-common.dtsi are

`serial@3100000 {
	compatible = "nvidia,tegra186-hsuart";
	status = "okay";
};

serial@3140000 {
	compatible = "nvidia,tegra186-hsuart";
	status = "okay";
};

combined-uart {
	console-port;
	combined-uart;
	status = "okay";
};`

tegra194-p3509-0000-a00.dtsi:
serial@3110000 { status = "okay"; };

dmesg THS devices as below

 ` [    1.616093] 3100000.serial: ttyTHS0 at MMIO 0x3100000 (irq = 47, base_baud = 0) is a TEGRA_UART

   [    1.617093] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 48, base_baud = 0) is a TEGRA_UART

   [    1.617781] 3140000.serial: ttyTHS4 at MMIO 0x3140000 (irq = 49, base_baud = 0) is a TEGRA_UART`

the console log actually output from ttyTHS0
does it means THS0 is UART3 pin 236 ,238 ( actual console output of our board is from UART1 pin 203~209)?
What should be the default related settings mapping between THS0 THS1 THS4 with uart1,uart2,uart3 in table 10-7
It seems doesnt meet the spec shows (console output from pin 236 238)

qbic-desktop login: Ubuntu 18.04.4 LTS qbic-desktop ttyTHS0

Can I redirect console to pin 236 238.? Thanks

hello Wiser.Kuo,

your console logs from ttyTHS0 were actually using pin-203/pin-205 for UART transmit.
please refer to below for an example,
according to device tree definition, serial@3100000 register as uart-a

	aliases {
		serial0 = &uarta;
...
	uarta: serial@3100000 {
		compatible = "nvidia,tegra186-hsuart";

you may also realize there’re module pin name and signal naming;
you should also check pinmux spreadsheets or the pinmux configuration file for reference.
for example,
$OUT/Linux_for_Tegra/bootloader/tegra19x-mb1-pinmux-p3668-a01.cfg

pinmux.0x024300a8 = 0x00000400; # uart1_tx_pr2: uarta, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x024300a0 = 0x00000454; # uart1_rx_pr3: uarta, pull-down, tristate-enable, input-enable, io_high_voltage-disable, lpdr-disable

BTW,
it’s serial kernel drivers to register tty device during kernel initialization, you may check below sources for more details.
i.e. $ L4T_Sources/r32.4.3/Linux_for_Tegra/source/public/kernel/kernel-4.9/drivers/tty/serial/serial_core.c

Hi Jerry:
Thanks , these info are very helpful.
but i still encounter some problem.
by follow your reply.
these are the uart mapping on L4T

tegra19x-mb1-pinmux-p3668-a01.cfg

pinmux.0x024300a8 = 0x00000400; # uart1_tx_pr2: uarta, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x024300a0 = 0x00000454; # uart1_rx_pr3: uarta, pull-down, tristate-enable, input-enable, io_high_voltage-disable, lpdr-disable
pinmux.0x02430098 = 0x00000055; # uart1_rts_pr4: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable
pinmux.0x02430090 = 0x00000055; # uart1_cts_pr5: rsvd1, pull-down, tristate-enable, input-enable, lpdr-disable

pinmux.0x0243d070 = 0x00000400; # uart2_tx_px4: uartb, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0243d078 = 0x00000450; # uart2_rx_px5: uartb, tristate-enable, input-enable, io_high_voltage-disable, lpdr-disable
pinmux.0x0243d080 = 0x00000408; # uart2_rts_px6: uartb, pull-up, tristate-disable, input-disable, lpdr-disable
pinmux.0x0243d088 = 0x00000458; # uart2_cts_px7: uartb, pull-up, tristate-enable, input-enable, lpdr-disable

pinmux.0x0c302010 = 0x00000400; # uart3_tx_pcc5: uartc, tristate-disable, input-disable, io_high_voltage-disable, lpdr-disable
pinmux.0x0c302008 = 0x00000450; # uart3_rx_pcc6: uartc, tristate-enable, input-enable, io_high_voltage-disable, lpdr-disable

pinmux spreadsheets

UART1_TXD 203 UART1_TX GPIO3_PR.02
UART1_RXD 205 UART1_RX GPIO3_PR.03
UART1_RTS* 207 UART1_RTS GPIO3_PR.04
UART1_CTS* 209 UART1_CTS GPIO3_PR.05

UART2_TXD 236 UART3_TX GPIO3_PCC.05
UART2_RXD 238 UART3_RX GPIO3_PCC.06

tegra194-soc-uart.dtsi

  serial0 = &uarta;
  serial1 = &uartb;
  serial2 = &uartc;

I enable all these uart , log:

[    1.437891] 3100000.serial: ttyTHS0 at MMIO 0x3100000 (irq = 47, base_baud = 0) is a TEGRA_UART
[    1.439066] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 48, base_baud = 0) is a TEGRA_UART
[    1.441064] c280000.serial: ttyTHS2 at MMIO 0xc280000 (irq = 49, base_baud = 0) is a TEGRA_UART
[    1.441848] 3130000.serial: ttyTHS3 at MMIO 0x3130000 (irq = 50, base_baud = 0) is a TEGRA_UART
[    1.442556] 3140000.serial: ttyTHS4 at MMIO 0x3140000 (irq = 51, base_baud = 0) is a TEGRA_UART
[    1.443210] 3150000.serial: ttyTHS5 at MMIO 0x3150000 (irq = 52, base_baud = 0) is a TEGRA_UART
[    1.444184] c290000.serial: ttyTHS6 at MMIO 0xc290000 (irq = 53, base_baud = 0) is a TEGRA_UART
[    1.444902] 3170000.serial: ttyTHS7 at MMIO 0x3170000 (irq = 54, base_baud = 0) is a TEGRA_UART

according to above info ,

THS0 =uarta=pr2/pr3=203/205 UART1_TX UART1_RX
THS2=uartc=pcc5/pcc6=236/238 UART3_TX UART3_RX

Since we design UART3 on pin header of our carrier board.
I open the terminal to output message to /dev/ttyTHS2 for test , and use oscilloscope to monitor UART3_TX signal. (pin236)
there are no any output signal , so as using rs232-usb cable with PC.

Is it any conflict pinmux setting on UART3 ? Or I miss other modification to make it work?

hello Wiser.Kuo,

please check NX Developer Kit User Guide and also refer to Topic 143741.
you may wiring uart transmit with J14, check “ll /dev/ttyUSB*” to setup connections.
thanks

Hi Jerry:
J14 Pins3/4 = UART2_TXD,UART2_RXD /UART3_TX,UART3_RX =pin 236,238
The port is mapping to ttyTHS2.
After HW debug , this port is available for general uart usage after kenel bootup

But booloader and lk log are output from this port. (THS2 , UART2_TXD,UART2_RXD)
And ttyTCU0 login console is binding with THS0 .

Is there any way to redirect ttyTCU0 also with THS2?
let THS0 (UART1_TXD UART1_RXD) remain clear for general uart usage?
Does it need to modify cboot source code?
I have tried to disable console by follow this thread

but it seems have no effect on NX , the console still output.

hello Wiser.Kuo,

you may disable kernel messages with the following configuration updates.
$OUT/Linux_for_Tegra/bootloader/t186ref/BCT/tegra194-mb1-bct-misc-l4t.cfg

enable_combined_uart = 0;
spe_uart_instance = 0xff;

furthermore, if you would like to disable bootloader messages;
please modify the Verbosity property, and then update the board configuration files by flashing the board.
$OUT/Linux_for_Tegra/bootloader/t186ref/BCT/tegra194-mb1-soft-fuses-l4t.cfg

Verbosity = 0; # 0: Disabled: 1: Critical, 2: Error, 3: Warn, 4: Info, 5: Debug

Hi , Jerry,
$OUT/Linux_for_Tegra/bootloader/t186ref/BCT/tegra194-mb1-bct-misc-l4t.cfg
after I modified and flashed , NX cant boot properly.
below is the bootloader messages output from THS2.

??
[0000.024] W> RATCHET: MB1 binary ratchet value 4 is too large than ratchet level 2 from HW fuses.
[0000.033] I> MB1 (prd-version: 1.5.1.3-t194-41334769-d2a21c57)
[0000.038] I> Boot-mode: Coldboot
[0000.041] I> Chip revision : A02P
[0000.044] I> Bootrom patch version : 15 (correctly patched)
[0000.049] I> ATE fuse revision : 0x200
[0000.053] I> Ram repair fuse : 0x1
[0000.056] I> Ram Code : 0x0
[0000.059] I> rst_source : 0x0
[0000.061] I> rst_level : 0x0
[0000.065] I> Boot-device: QSPI
[0000.068] I> Qspi flash params source = brbct
[0000.072] I> Qspi using bpmp-dma
[0000.075] I> Qspi clock source : pllp
[0000.078] I> QSPI Flash Size = 32 MB
[0000.081] I> Qspi initialized successfully
[0000.085] W> No valid slot number is found in scratch register
[0000.091] W> Return default slot: _a
[0000.094] I> Active Boot chain : 0
[0000.097] I> Boot-device: QSPI
[0000.100] I> Qspi flash params source = brbct
[0000.106] W> MB1_PLATFORM_CONFIG: device prod data is empty in MB1 BCT.
[0000.114] I> Temperature = 65000
[0000.117] W> Skipping boost for clk: BPMP_CPU_NIC
[0000.121] W> Skipping boost for clk: BPMP_APB
[0000.125] W> Skipping boost for clk: AXI_CBB
[0000.129] W> Skipping boost for clk: AON_CPU_NIC
[0000.133] W> Skipping boost for clk: CAN1
[0000.137] W> Skipping boost for clk: CAN2
[0000.141] I> Boot-device: QSPI
[0000.144] I> Boot-device: QSPI
[0000.147] I> Qspi flash params source = mb1bct
[0000.151] I> Qspi using bpmp-dma
[0000.154] I> Qspi clock source : pllc_out0
[0000.158] I> Qspi reinitialized
[0000.161] I> Qspi flash params source = mb1bct
[0000.166] I> ECC region[0]: Start:0x0, End:0x0
[0000.170] I> ECC region[1]: Start:0x0, End:0x0
[0000.174] I> ECC region[2]: Start:0x0, End:0x0
[0000.178] I> ECC region[3]: Start:0x0, End:0x0
[0000.182] I> ECC region[4]: Start:0x0, End:0x0
[0000.187] I> Non-ECC region[0]: Start:0x80000000, End:0x100000000
[0000.192] I> Non-ECC region[1]: Start:0x0, End:0x0
[0000.197] I> Non-ECC region[2]: Start:0x0, End:0x0
[0000.201] I> Non-ECC region[3]: Start:0x0, End:0x0
[0000.206] I> Non-ECC region[4]: Start:0x0, End:0x0
[0000.211] E> FAILED: Thermal config
[0000.218] E> FAILED: MEMIO rail config
[0000.229] I> Boot-device: QSPI
[0000.232] I> Qspi flash params source = mb1bct
[0000.241] I> Qspi flash params source = mb1bct
[0000.252] I> Qspi flash params source = mb1bct
[0000.319] I> Qspi flash params source = mb1bct
[0000.328] I> Qspi flash params source = mb1bct
[0000.355] I> Qspi flash params source = mb1bct
[0000.367] I> MB1 done

[0000.375] I> Welcome to MB2(TBoot-BPMP) (version: 00.00.2018.32-mobile-2dfe4beb)
[0000.382] I> DMA Heap @ [0x526fa000 - 0x52ffa000]
[0000.387] I> Default Heap @ [0xd486400 - 0xd48a400]
[0000.392] E> DEVICE_PROD: Invalid value data = 70020000, size = 0.
[0000.398] W> device prod register failed
[0000.402] I> Boot-device: QSPI
[0000.405] I> Boot_device: QSPI_FLASH instance: 0
[0000.410] I> QSPI Flash Size = 32 MB
[0000.416] I> Qspi initialized successfully
[0000.420] I> qspi flash-0 params source = boot args
[0000.803] I> sdmmc DDR50 mode
[0000.808] I> sdmmc-3 params source = safe params
[0000.815] I> Found 47 partitions in QSPI_FLASH (instance 0)
[0000.822] W> Cannot find any partition table for 00000003
[0000.829] I> Found 11 partitions in SDMMC_USER (instance 3)
[0000.835] W> No valid slot number is found in scratch register
[0000.841] W> Return default slot: _a
[0000.844] I> Active Boot chain : 0
[0000.848] I> parsing oem signed section of bpmp-fw header done
[0000.854] I> bpmp-fw binary init read from storage
[0000.859] I> oem authentication of bpmp-fw header done
[0000.874] I> bpmp-fw binary done read from storage
[0000.879] I> bpmp-fw: Authentication init Done
[0000.884] I> parsing oem signed section of cpubl header done
[0000.889] I> cpubl binary init read from storage
[0000.894] I> bpmp-fw: Authentication Finalize Done
[0000.899] I> oem authentication of cpubl header done
[0000.906] I> cpubl binary done read from storage
[0000.911] I> cpubl: Authentication init Done
[0000.915] I> parsing oem signed section of rce header done
[0000.921] I> rce binary init read from storage
[0000.926] I> Relocating BR-BCT
[0000.929] I> cpubl: Authentication Finalize Done
[0000.934] I> oem authentication of rce header done
[0000.939] I> rce binary done read from storage
[0000.943] I> rce: Authentication init Done
[0000.948] I> parsing oem signed section of ape header done
[0000.954] I> ape binary init read from storage
[0000.958] I> rce: Authentication Finalize Done
[0000.963] I> oem authentication of ape header done
[0000.968] I> ape binary done read from storage
[0000.972] I> ape: Authentication init Done
[0000.977] I> parsing oem signed section of tos header done
[0000.982] I> tos binary init read from storage
[0000.987] I> ape: Authentication Finalize Done
[0000.992] I> oem authentication of tos header done
[0000.998] I> tos binary done read from storage
[0001.003] I> tos: Authentication init Done
[0001.007] I> parsing oem signed section of bpmp-fw-dtb header done
[0001.014] I> bpmp-fw-dtb binary init read from storage
[0001.019] I> tos: Authentication Finalize Done
[0001.025] I> oem authentication of bpmp-fw-dtb header done
[0001.030] I> bpmp-fw-dtb binary done read from storage
[0001.035] I> bpmp-fw-dtb: Authentication init Done
[0001.040] I> parsing oem signed section of cpubl-dtb header done
[0001.047] I> cpubl-dtb binary init read from storage
[0001.052] I> bpmp-fw-dtb: Authentication Finalize Done
[0001.098] I> oem authentication of cpubl-dtb header done
[0001.104] I> cpubl-dtb binary done read from storage
[0001.109] I> cpubl-dtb: Authentication init Done
[0001.114] I> parsing oem signed section of eks header done
[0001.119] I> eks binary init read from storage
[0001.124] I> cpubl-dtb: Authentication Finalize Done
[0001.129] I> oem authentication of eks header done
[0001.134] I> eks binary done read from storage
[0001.138] I> eks: Authentication init Done
[0001.142] I> eks: Authentication Finalize Done
[0001.147] I> EKB detected (length: 0x410) @ VA:0x52714400
ipc-unittest-main: 1519: Welcome to IPC unittest!!!
ipc-unittest-main: 1531: waiting forever
ipc-unittest-srv: 329: Init unittest services!!!
hwkey-agent: 40: hwkey-agent is running!!
hwkey-agent: 182: key_mgnt_processing …
hwkey-agent: 157: Init hweky-agent services!!
platform_bootstrap_epilog: trusty bootstrap complete

Compare to bootable logs , it seems NX can’t boot into lk.

If kernel message can be disabled .
Can it be redirect to THS2 ? Let it ouput kernel messages and bootloader messages at the same port.

Update…
The “Verbosity = 0” bootloader solution works partially. Since lk messages still ouput , only bootloader messages has been disabled. ( console should output ,or it will not boot.)

hello Wiser.Kuo,

please refer to Topic 54744 for the steps to switch uart instance.

After my test with privious settings for turn off logs

enable_combined_uart = 0;
spe_uart_instance = 0xff;

Verbosity = 0; # 0: Disabled: 1: Critical, 2: Error, 3: Warn, 4: Info, 5: Debug

System will stuck at bootloader if turn kernel log off
System will boot properly if turn off bootloader message and keep kernel log on.

In Xavier NX mb1 misc config, it does’t have those settings to be modified

debug.enable_log = 1;
-debug.uart_instance = 0;
+debug.uart_instance = 2;

Instead , it uses combine uart feature ,seems logs are come from ttyTCU0 along with ttyTHS0 port

enable_combined_uart = 1;
spe_uart_instance = 0x2;
Does it uses other way to change console log uart or close tegra-combine-uart feature ?

Are you sure the “console=ttyTCU0” has been removed in kernel cmdline?

I tried to change “console=ttyTCU0” to “console=ttyTHS2” in tegra194-p3668-common.dtsi
seems no affect to combine uart.
It still show ttyTHS0 at login section (connect UART1=ttyTHS2 to see these messages…)

qbic-desktop login: qbic
Password:
Last login: 五 八 7 17:24:12 CST 2020 on ttyTHS0
Welcome to Ubuntu 18.04.4 LTS (GNU/Linux 4.9.140+ aarch64)

This system has been minimized by removing packages and content that are
not required on a system that users do not log into.

To restore this content, you can run the ‘unminimize’ command.

190 packages can be updated.
132 updates are security updates.

To run a command as administrator (user “root”), use “sudo ”.
See “man sudo_root” for details.

qbic@qbic-desktop:~$
qbic@qbic-desktop:~$
qbic@qbic-desktop:~$
qbic@qbic-desktop:~$
qbic@qbic-desktop:~$
qbic@qbic-desktop:~$ dmesg
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.9.140+ (root@skyangel) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05) ) #1 SMP PREEMPT Fri Jul 24 14:03:01 CST 2020
[ 0.000000] Boot CPU: AArch64 Processor [4e0f0040]
[ 0.000000] OF: fdt:memory scan node memory, reg size 48,
[ 0.000000] OF: fdt: - 80000000 , 2c000000
[ 0.000000] OF: fdt: - ac200000 , 44600000
[ 0.000000] OF: fdt: - 100000000 , 180000000
[ 0.000000] earlycon: tegra_comb_uart0 at MMIO32 0x000000000c168000 (options ‘’)
[ 0.000000] bootconsole [tegra_comb_uart0] enabled
[ 0.000000] Found tegra_fbmem: 00800000@a069d000
[ 0.000000] Found lut_mem: 00002008@a0697000
[ 0.000000] OF: fdt:Reserved memory: failed to reserve memory for node ‘fb1_carveout’: base 0x0000000000000000, size 0 MiB
[ 0.000000] OF: fdt:Reserved memory: failed to reserve memory for node ‘fb1_carveout’: base 0x0000000000000000, size 0 MiB
[ 0.000000] OF: fdt:Reserved memory: failed to reserve memory for node ‘fb2_carveout’: base 0x0000000000000000, size 0 MiB
[ 0.000000] OF: fdt:Reserved memory: failed to reserve memory for node ‘fb2_carveout’: base 0x0000000000000000, size 0 MiB
[ 0.000000] OF: fdt:Reserved memory: failed to reserve memory for node ‘fb3_carveout’: base 0x0000000000000000, size 0 MiB
[ 0.000000] OF: fdt:Reserved memory: failed to reserve memory for node ‘fb3_carveout’: base 0x0000000000000000, size 0 MiB
[ 0.000000] OF: reserved mem: initialized node ramoops_carveout, compatible id nvidia,ramoops
[ 0.000000] OF: reserved mem: initialized node vpr-carveout, compatible id nvidia,vpr-carveout
[ 0.000000] OF: reserved mem: initialized node grid-of-semaphores, compatible id nvidia,gosmem
[ 0.000000] cma: Reserved 64 MiB at 0x00000000c2000000
[ 0.000000] On node 0 totalpages: 2030589
[ 0.000000] DMA zone: 7152 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 457725 pages, LIFO batch:31
[ 0.000000] Normal zone: 24576 pages used for memmap
[ 0.000000] Normal zone: 1572864 pages, LIFO batch:31
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.0 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.1
[ 0.000000] percpu: Embedded 25 pages/cpu @ffffffc1ffd13000 s61656 r8192 d32552 u102400
[ 0.000000] pcpu-alloc: s61656 r8192 d32552 u102400 alloc=25*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5
[ 0.000000] Speculative Store Bypass Disable mitigation not required
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1998861
[ 0.000000] Kernel command line: console=ttyTHS2,115200 video=tegrafb no_console_suspend=1 earlycon=tegra_comb_uart,mmio32,0x0c168000 gpt tegra_fbmem=0x800000@0xa069d000 lut_mem=0x2008@0xa0697000 usbcore.old_scheme_first=1 tegraid=19.1.2.0.0 maxcpus=6 boot.slot_suffix= boot.ratchetvalues=0.4.2 vpr_resize sdhci_tegra.en_boot_part_access=1 quiet root=/dev/mmcblk0p1 rw rootwait rootfstype=ext4 console=ttyTHS1,115200n8 fbcon=map:0 net.ifnames=0

Table 10-7 is not in the documentation anymore…

hello anthony.yan,

please access NX Product Design Guide, you may check for chapter [11.3 UART].
there’s Jetson Xavier NX UART pin descriptions in the beginning.
thanks

Thank you for the information.

I was reading deeper into the notes under table [11-7] in chapter [11.3 UART], specifically entry #2 about pins have GPIO functionality except for a few that default to UART. I am a bit confused whether pin 203 is as specified - default to be UART1_TXD or how to get UART working on 40-Pin Expansion Header.

I am having trouble receiving my own sent messages on different terminals (1. echo; 2. cat) when performing a simple loopback test by jumpering pin 8 and 10 on the 40-Pin Expansion Header which maps to pin 203 (UART1_TXD) and pin 205 (UART1_RXD). I also believe I have rw permission… I hope you can help shed some light on this issue. Thank you. image

hello anthony.yan,

you may looking for kernel messages to check the address of ttyTHS, and also refer to DT for its UART port.
please also check below topic for the mappings for serial ports of ttyTHS*, and UART* for reference,
i.e. Serial communication between Jetson nano and Arduino through GPIO - #5 by JerryChang.

1 Like