Disabling UART debug prints over ttyTCU0

Autonomous Machines Jetson & Embedded Systems Jetson Xavier NX
1

Hi,
I have seen many topics regarding the ability to completely disable debug printing from ttyTCU0, while I am not sure which steps are needed.
The motivation is the need for additional UART except ttyHS1 (40pin header). Since one of the UARTs is UART0 to M2, I have only the debug UART left (I would like to utilize the M2 uart, too, but for now even one more is enough).

Currently available uarts:

[    1.424639] 3100000.serial: ttyTHS0 at MMIO 0x3100000 (irq = 47, base_baud = 0) is a TEGRA_UART
[    1.425706] 3110000.serial: ttyTHS1 at MMIO 0x3110000 (irq = 48, base_baud = 0) is a TEGRA_UART
[    1.426569] 3140000.serial: ttyTHS4 at MMIO 0x3140000 (irq = 49, base_baud = 0) is a TEGRA_UART

1. SoC: UART1 = Jetson: UART1 `ttyTHS0`: for general use, UART General
2. SoC: UART2 = Jetson: UART0 `ttyTHS1`: for internal use (not available to user), M.2 Key E
3. SoC: UART3 = Jetson: UART2 `ttyTHS4`: for debugging, Debug UART

According to the above I assume ttyTCU0 = ttyTHS4?

I figured the relevant .dtb/.dts file by grepping “dmesg | grep dts”

tegra194-p3668-all-p3509-0000.dts

Followed the guides:

This one says it might not even be possible:

To disable the combined UART -

  1. Downloaded BSP sources, edited,
    sources/hardware/nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3668-common.dtsi
from:
	chosen {
		bootargs ="console=ttyTCU0,115200";
		board-has-eeprom;
		nvidia,tegra-joint_xpu_rail;
	};
	combined-uart {
		console-port;
		combined-uart;
		status = "okay";
	};
to:
	chosen {
		bootargs ="";
		board-has-eeprom;
		nvidia,tegra-joint_xpu_rail;
	};
	combined-uart {
		console-port;
		combined-uart;
		status = "disabled";
	};

After compiling, I replaced the output tegra194-p3668-common.dtb with the matching file -
kernel/dtb/tegra194-p3668-all-p3509-0000.dtb

  1. edited Linux_for_Tegra/p3668.conf.common
from:

CMDLINE_ADD="console=ttyTCU0,115200n8 console=tty0 fbcon=map:0 net.ifnames=0";

to:

CMDLINE_ADD="console=tty0 fbcon=map:0 net.ifnames=0";
  1. Changed both :
  • Linux_for_Tegra/bootloader/t186ref/BCT/tegra194-mb1-bct-misc-flash.cfg
  • Linux_for_Tegra/bootloader/t186ref/BCT/tegra194-mb1-bct-misc-l4t.cfg

NOTE: This change causes flash to fail which is aligned to this thread

from:
enable_combined_uart = 1;
spe_uart_instance = 2

to:
enable_combined_uart = 0;
spe_uart_instance = 0xff
  1. Could not find the source for bootloader/t186ref/tegra194-a02-bpmp-p3668-a00.dtb which requires edit according to some threads.

I am not sure what else do I need, just that step 3 causes everything to fail and it looks like a crucial step.

Any additional information would be very helpful.

Thanks,
Shauli

2 Likes
3

Hi shauli.arazi,

You could use dtc command to dissemble the dtb file.

$ dtc -I dtb -O dts -o tegra194-a02-bpmp-p3668-a00.dts tegra194-a02-bpmp-p3668-a00.dtb

After modification, assemble dts back to dtb

$ dtc -I dts -O dtb -o tegra194-a02-bpmp-p3668-a00.dtb tegra194-a02-bpmp-p3668-a00.dts

You could also try to add quiet in kernel cmdline as following:

CMDLINE_ADD="console=tty0 fbcon=map:0 net.ifnames=0 quiet";
4

Hi Kevin,
Thank you for responding.
Are all these steps (including editing the bpmp file) sufficient for disabling console debug over UART?
Also, any idea why changing step 3 causes the flashing to fail? maybe I do not need this step.
Regards,
Shauli

5

Sorry, there are no full guide to remove console log, it includes MB1/MB2/bootloader/kernel.
You could just follow current suggestion trying to disable them and see if it can meet your requirement.

They are configuration file for bpmp, modifying them should not cause flashing failed.
Are you sure the flashing failed caused from them?

6

Hopefully if I figure it out, people will find this thread a proper guide :)

I agree these are simply configuration files. However, as can be seen in this thread

Once I edit the configuration file, flashing is stuck at

[  14.8264 ] tegrarcm_v2 --isapplet

If you have a debug flag which I can use to see what is actually failing behind the scenes, I would gladly add it and post additional logs.

I opened this thread because I tried all the steps above except editing the BPMP file (which I will try very soon) and editing the configuration file since the flashing fails so I could not apply them and test.

Currently the console is disabled but it look like the UART interface is not working properly.

In addition to all these steps, are there any others steps I should try?

Thanks for finding the time to answer my questions.

7

What do you mean about "UART interface not working properly"?

and what’s your purpose to disable them?
Does the current state meet your requirement?

8

Hi Kevin,
I would like to use the UART interface which is currently occupied for debug as an interface for GPS.
By not working properly I mean I am not able to transfer bi-directional communication over TCU0.
Thanks,
Shauli

9

There should be other UART interfaces could be used.
Have you tried them for GPS usage?
Without debug UART messages, you would be hard to debug the board further.

10

I agree, however, the Xavier NX carrier board has 3 uarts in total, while only one is actually available.

1. SoC: UART1 = Jetson: UART1 `ttyTHS0`: for general use, UART General
2. SoC: UART2 = Jetson: UART0 `ttyTHS1`: for internal use (not available to user), M.2 Key E
3. SoC: UART3 = Jetson: UART2 `ttyTHS4`: for debugging, Debug UART

A single UART is not sufficient for me. I need at least one more. That’s why I’m trying to operationalize the debug UART.

11

Are you using the devkit or custom board for Xavier NX?

This UART should be available for user. Or do you mean the M.2 Key E already been used for other purpose?

1 Like
12

I am using the devkit.

Following the board schematics, I have not observed any pins that expose UART0 in the devkit carrier.

14

The UART0 pins are listed in Table 2-7. M.2, Key E Expansion Slot Pin Description – J10 in your pasted spec.

1 Like
15

Hi Trumany,
J10 is occupied for a WIFI extension card. Even if I removed the card it is not as accessible as the other 2 UARTS.
I need the debug console UART. There is no way around this.

18

Do you mean all data could not be sent/received or just missing some packets?
Is there still any debug message output?

What do you mean about “not as accessible”? no pins available there?

20

@shauli.arazi Nice work dragging all of these separate threads together.

I’m in a similar position as you, looking to get all 3 UARTS setup for general purpose use. With no bootloader output on UART2.

I’d previously followed the snippets from elsewhere and have just given your notes a go.

Using JetPack 5.0.2 which contains Jetson Linux 35.1.

Didn’t encounter the flashing issue this time, although I did while following other posts previously. flash.sh would just lockup at some point.

For step 4 I was able to disassemble, modify and re-assemble the dtb file with the included dtc tool. From the Linux_For_Tegra directory:

./kernel/dtc -I dts -O dtb -o ./bootloader/t186ref/tegra194-a02-bpmp-p3668-a00.dtb ./bootloader/t186ref/tegra194-a02-bpmp-p3668-a00.dts

Edit tegra194-a02-bpmp-p3668-a00.dts.

I updated:

        serial {
                port = <0x3>;
                has_input;

                combined-uart {
                        disabled;
                };
        };

To:

        serial {
                port = <0x2>;
                has_input;
        };

As suggested by one of the other posts.

Reassemble:

./kernel/dtc -I dts -O dtb -o ./bootloader/t186ref/tegra194-a02-bpmp-p3668-a00.dtb ./bootloader/t186ref/tegra194-a02-bpmp-p3668-a00.dts

Flashing this went well, but unfortunately results in the unit getting stuck during booting. While also not disabling the bootloader output on UART2.

Here’s from poweron to getting stuck:

[0000.025] W> RATCHET: MB1 binary ratchet value 4 is larger than ratchet level 2 from HW fuses.
[0000.033] I> MB1 (prd-version: 2.3.0.0-t194-41334769-0a17edc1)
[0000.038] I> Boot-mode: Coldboot
[0000.041] I> Platform: Silicon
[0000.044] I> Chip revision : A02P
[0000.047] I> Bootrom patch version : 15 (correctly patched)
[0000.052] I> ATE fuse revision : 0x200
[0000.056] I> Ram repair fuse : 0x1
[0000.059] I> Ram Code : 0x2
[0000.061] I> rst_source: 0x0, rst_level: 0x0
[0000.066] I> Boot-device: QSPI (instance: 0)
[0000.070] I> Qspi flash params source = brbct
[0000.074] I> Qspi clock source : pllp
[0000.078] I> Qspi-0 initialized successfully
[0000.081] I> Boot chain mechanism: A/B
[0000.085] I> Current Boot-Chain Slot: 0
[0000.088] I> BR-BCT Boot-Chain: 0, status: 0. update flag: 0
[0000.094] I> Qspi flash params source = brbct
[0000.100] W> PROD_CONFIG: device prod data is empty in MB1 BCT.
[0000.107] I> Temperature = 29500
[0000.110] W> Skipping boost for clk: BPMP_CPU_NIC
[0000.114] W> Skipping boost for clk: BPMP_APB
[0000.118] W> Skipping boost for clk: AXI_CBB
[0000.122] W> Skipping boost for clk: AON_CPU_NIC
[0000.126] W> Skipping boost for clk: CAN1
[0000.130] W> Skipping boost for clk: CAN2
[0000.134] I> Boot-device: QSPI (instance: 0)
[0000.138] I> Qspi flash params source = mb1bct
[0000.142] I> Qspi clock source : pllc_out0
[0000.146] I> Qspi-0 reinitialized
[0000.149] I> Qspi flash params source = mb1bct
[0000.162] I> Non-ECC region[0]: Start:0x80000000, End:0x100000000
[0000.169] W>  Thermal config not found in BCT
[0000.177] W>  MEMIO rail config not found in BCT
[0000.189] I> Qspi flash params source = mb1bct
[0000.202] I> Qspi flash params source = mb1bct
[0000.236] I> Qspi flash params source = mb1bct
[0000.800] I> Qspi flash params source = mb1bct
[0000.817] I> Qspi flash params source = mb1bct
[0000.856] W>  Platform config not found in BCT
[0000.883] I> Qspi flash params source = mb1bct
[0000.908] I> MB1 done

[0000.917] I> Welcome to MB2(TBoot-BPMP) (version: default.t194-mobile-1ca012e4)
[0000.924] I> DMA Heap @ [0x526fa000 - 0x52ffa000]
[0000.929] I> Default Heap @ [0xd486400 - 0xd48a400]
[0000.934] E> DEVICE_PROD: Invalid value data = 70020000, size = 0.
[0000.940] W> device prod register failed
[0000.943] I> gpio framework initialized
[0000.947] I> tegrabl_gpio_driver_register: register 'nvidia,tegra194-gpio' driver
[0000.954] I> tegrabl_gpio_driver_register: register 'nvidia,tegra194-gpio-aon' driver
[0000.961] I> No valid sdcard_params in mb1_bct
[0000.966] I> Boot_device: QSPI_FLASH instance: 0
[0000.970] I> qspi flash-0 params source = boot args
[0000.975] I> QSPI-0l initialized successfully
[0000.979] I> sdmmc-3 params source = safe params
[0001.399] I> sdmmc DDR50 mode
[0001.419] I> Found 41 partitions in QSPI_FLASH (instance 0)
[0001.441] W> Cannot find any partition table for 00000003
[0001.446]  > PARTITION_MANAGER: Failed to publish partition.
[0001.467] I> Found 19 partitions in SDMMC_USER (instance 3)
[0001.473] I> Active Boot chain : 0
[0002.147] I> Relocating BR-BCT
[0002.150]  > DEVICE_PROD: device prod is not initialized.
[0002.461] I> Relocating OP-TEE dtb from: 0x6bfff1d0 to 0x70050000, size: 1008
[0002.468] I> [0] START: 0x80000000, SIZE: 0x2f000000
[0002.472] I> [1] START: 0xaf010000, SIZE: 0x18bf0000
[0002.477] I> [2] START: 0xc7d00000, SIZE: 0xc0000
[0002.481] I> [3] START: 0xca000000, SIZE: 0x800000
[0002.486] I> dram_block larger than 80000000
[0002.490] I> [4] START: 0x100000000, SIZE: 0x380000000
[0002.501] I> Setting NS memory ranges to OP-TEE dtb finished.
[0002.510] I> found decompressor handler: lz4
[0002.904] I> EKB detected (length: 0x410) @ VA:0x52709400
[0002.910] I> Setting EKB blob info to OPTEE dtb finished.
[0009.476] I> Welcome to NVDisp-Init
[0009.479] I> NVDisp-Init version: t194-f9ecfedc
[0009.483] I> CPU-BL Params @ 0xca020000
[0009.487] I>  0) Base:0x00000000 Size:0x00000000
[0009.491] I>  1) Base:0xc8300000 Size:0x00100000
[0009.495] I>  2) Base:0xc9800000 Size:0x00200000
[0009.499] I>  3) Base:0xc8600000 Size:0x00200000
[0009.504] I>  4) Base:0xc8200000 Size:0x00100000
[0009.508] I>  5) Base:0xc8100000 Size:0x00100000
[0009.512] I>  6) Base:0xc9400000 Size:0x00400000
[0009.516] I>  7) Base:0xc9000000 Size:0x00400000
[0009.521] I>  8) Base:0xc8000000 Size:0x00100000
[0009.525] I>  9) Base:0xc7f00000 Size:0x00100000
[0009.529] I> 10) Base:0xca800000 Size:0x00800000
[0009.533] I> 11) Base:0x40000000 Size:0x00040000
[0009.538] I> 12) Base:0xc7e00000 Size:0x00100000
[0009.542] I> 13) Base:0x40046000 Size:0x00002000
[0009.546] I> 14) Base:0x40048000 Size:0x00002000
[0009.550] I> 15) Base:0xaf000000 Size:0x00004000
[0009.555] I> 16) Base:0x4004a000 Size:0x00002000
[0009.559] I> 17) Base:0xc7c00000 Size:0x00100000
[0009.563] I> 18) Base:0x4004c000 Size:0x00002000
[0009.567] I> 19) Base:0xc9a00000 Size:0x00600000
[0009.572] I> 20) Base:0x4004e000 Size:0x00002000
[0009.576] I> 21) Base:0xc7dc0000 Size:0x0000c000
[0009.580] I> 22) Base:0x00000000 Size:0x00000000
[0009.585] I> 23) Base:0xc7de0000 Size:0x00020000
[0009.589] I> 24) Base:0xcc000000 Size:0x02000000
[0009.593] I> 25) Base:0x40050000 Size:0x00002000
[0009.597] I> 26) Base:0x40040000 Size:0x00006000
[0009.602] I> 27) Base:0xc8c00000 Size:0x00400000
[0009.606] I> 28) Base:0xc8400000 Size:0x00200000
[0009.610] I> 29) Base:0xc8800000 Size:0x00400000
[0009.614] I> 30) Base:0xc7dd0000 Size:0x00010000
[0009.619] I> 31) Base:0x00000000 Size:0x00000000
[0009.623] I> 32) Base:0xf8000000 Size:0x08000000
[0009.627] I> 33) Base:0xce000000 Size:0x2a000000
[0009.631] I> 34) Base:0xcb000000 Size:0x01000000
[0009.636] I> 35) Base:0xae000000 Size:0x01000000
[0009.640] I> 36) Base:0xa0000000 Size:0x0e000000
[0009.644] I> 37) Base:0xca000000 Size:0x00800000
[0009.648] I> 38) Base:0x80000000 Size:0x20000000
[0009.653] I> 39) Base:0xb0000000 Size:0x08000000
[0009.657] I> 40) Base:0x00000000 Size:0x00000000
[0009.661] I> 41) Base:0x00000000 Size:0x00000000
[0009.665] I> 42) Base:0x00000000 Size:0x00000000
[0009.670] I> 43) Base:0x00000000 Size:0x00000000
[0009.674] I> 44) Base:0x00000000 Size:0x00000000
[0009.678] I> 45) Base:0x00000000 Size:0x00000000
[0009.683] GIC-SPI Target CPU: 0
[0009.686] Interrupts Init done
[0009.689] calling constructors
[0009.692] initializing heap
[0009.694] I> Heap: [0xa0960000 ... 0xadf00000]
[0009.698] initializing threads
[0009.701] initializing timers
[0009.704] creating bootstrap completion thread
[0009.709] top of bootstrap2()
[0009.712] CPU: MIDR: 0x4E0F0040, MPIDR: 0x80000000
[0009.717] initializing platform
[0009.720] E> DEVICE_PROD: Invalid value data = 0, size = 0.
[0009.725] W> device prod register failed
[0009.729] I> Bl_dtb @0xadf00000
[0009.732] I> gpio framework initialized
[0009.742] I> tegrabl_gpio_driver_register: register 'nvidia,tegra194-gpio' driver
[0009.752] I> tegrabl_gpio_driver_register: register 'nvidia,tegra194-gpio-aon' driver
[0009.763] I> fixed regulator driver initialized
[0009.783] I> register 'maxim' power off handle
[0009.789] I> virtual i2c enabled
[0009.792] I> registered 'maxim,max20024' pmic
[0009.797] I> tegrabl_gpio_driver_register: register 'max20024-gpio' driver
[0009.803] I> Boot-device: QSPI
[0009.806] I> Boot_device: QSPI_FLASH instance: 0
[0009.810] I> configure_qspi_clk: qparams clk_src = 5, clk_div = 0, clk_src_freq = 800000000, interface_freq = 50000000
[0009.820] I> configure_qspi_clk: FORCING INTERFACE_FREQ TO 133000000!!
[0009.827] I> QSPI source rate = 204000 Khz
[0009.831] I> Requested rate for QSPI clock = 34000 Khz
[0009.836] I> BPMP-set rate for QSPI clk = 34000 Khz
[0009.841] I> tx_clk_tap_delay : 0
[0009.844] I> rx_clk_tap_delay : 16
[0009.847] I> QSPI Flash Size = 32 MB
[0009.854] I> Qspi initialized successfully
[0009.858] I> qspi flash-0 params source = boot args
[0009.863] W> No board IDs available
[0009.866] E> Failed to get board id info!
[0009.872] I> sdmmc-3 params source = safe params
[0009.881] I> Found 41 partitions in QSPI_FLASH (instance 0)
[0009.887] W> Cannot find any partition table for 00000003
[0009.892] E> Failed to publish 00000003
[0009.901] I> Found 19 partitions in SDMMC_USER (instance 3)
[0009.921] I> regulator 'vdd-hdmi-5v0' already enabled
[0009.932] I> regulator 'vdd-hdmi-5v0' already enabled
[0009.936] I> hdmi cable connected
[0009.944] W> set volts not configured for 'vdd-1v0'
[0009.952] W> set volts not configured for 'vdd-1v8-hs'
[0009.957] I> retrieved tmds range from prod_list_hdmi_soc
[0009.967] E> invalid display type
[0009.971] E> cannot find any other nvdisp nodes
[0009.991] I> edid read success
[0010.006] I> edid read success
[0010.008] I> width = 640, height = 480, frequency = 25174825
[0010.014] I> width = 640, height = 480, frequency = 25174825
[0010.019] I> width = 1920, height = 1080, frequency = 148500000
[0010.024] I> width = 1920, height = 1080, frequency = 148500000
[0010.030] I> width = 1920, height = 1080, frequency = 148351648
[0010.036] I> width = 1920, height = 1080, frequency = 148351648
[0010.041] I> width = 1280, height = 720, frequency = 74175824
[0010.046] I> width = 1280, height = 720, frequency = 74175824
[0010.052] I> width = 720, height = 480, frequency = 26973026
[0010.057] I> width = 720, height = 576, frequency = 26973026
[0010.062] I> width = 720, height = 480, frequency = 26973026
[0010.067] I> width = 720, height = 576, frequency = 26973026
[0010.073] I> width = 640, height = 480, frequency = 25174825
[0010.078] I> Best mode Width = 1920, Height = 1080, freq = 148351648
[0010.089] I> hdmi_enable, starting HDMI initialisation
[0010.098] I> hdmi_enable, HDMI initialisation complete
[0010.112] initializing target
[0010.114] calling apps_init()
[0010.117] starting app kernel_boot_app
[0010.121] I> Kernel type = Normal

I’ll share any progress I make here but its not looking good a present.

Annoyingly we accidentally selected UART2 as the main UART on our customer’s carrier board. Didn’t realise at the time that it was fundamentally different the to the other two and would be a nightmare to disable the tegra combined-uart.

Regards,

Phil

1 Like
21

Hi Kevin,
What do you mean about “not as accessible”? no pins available there?
It is a M2 connection which requires soldering, unlike the other 2 UARTS which have their headers exposed for simplicity. Regardless, it is currently used for a WIFI component

image
image921Ă—629 43.2 KB

Do you mean all data could not be sent/received or just missing some packets?
Is there still any debug message output?
I was only able to push traffic, not receive. I need to sanity check this again as I had so many modification and I might have done something wrong.

22

Hi Phil,
Thanks for taking the time to add information to this thread.
I trying to use an off-the-shelf carrier board in parallel to the devkit. I did manage to get the debug UART to work by changing the bootargs in /boot/extlinux/extlinux.conf to not include any “console=ttyTCU0,115200n8” statements.
While there is still output during boot, I am able to use the UART when the boot is done. I am still using ttyTCU0.
Unfortunately, this does not work with the devkit, so I had to resort to changing device tree.
What I did see is that changing the .DTS caused the ttyTCU0 to disappear, while no other ttyTH* became functional.
Regarding the bpmp changes, I was wondering what changing the port = <0x3> to <0x2> does.
Thanks,
Shauli

23

I’ve been using a this WaveShare carrier board which has the debug UART broken out on the single row header under the Jetson board:

Found that editing the command line arguments in /boot/extlinux/extlinux.conf was enough to silence the kernel output during boot and disable the console.

Then as you suggested using /dev/ttyTCU0 seems to work ok.

I wasn’t sure what the impact of the combined uart module was though. For example when for example changing baud rates or sending binary data.

I understand that the combined UART multiplexes data from the different processors onboard, so presumably includes some sort of delimiter or escape sequence. I’m wondering if there would be certain data which would be escaped by the multiplexing and therefore appear corrupt when it arrives at the remote device.

In terms of what the port = <0x3> to <0x2> does…no idea I’m afraid. Maybe someone from NVIDIA will be able to provide us with some more info?

Regards,

Phil

25

Hi Phil,
Would you kindly share /proc/cmdline? I would like to see what actually runs to understand why I still see boot output. Did you edit the DTS and change extlinux.conf? or simply change the conf file?
My current issue is that editing the conf file is not enough as I am only able to push data from the UART, but nothing is received.
I should also mention that this happens with the DevKit carrier only.
Thanks,
Shauli

26

Hi Shauli,

I haven’t tried reception myself yet.

Will be back working on this again on Friday, will try rx and grab the command line arguments for you.

I didn’t perform any other DTS changes when trying it before, just removed ttyTCU0 from the kernel cmdline.

Thanks,

Phil

1 Like