AGX Xavier enable uartg/uart7

I’m trying to enable uartg/uart7 on Jetson AGX Xavier devkit with R32 (release), REVISION: 5.1 to manually connect a serial device to the respective PCI-E pins.

Therefore I have changed pinmux of SPI2 pins via Excel tool, which resulted in a modified bootloader/t186ref/BCT/tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg. Then, flashing with ./ -k MB1_BCT jetson-agx-xavier-devkit mmcblk0p1 makes the readout of /sys/kernel/debug/tegra_pinctrl_reg change, so I expect it to be successful.
Still, I don’t get a serial device on 0x0c290000 and believe , I need to enable the driver for it. I tried doing that by modifying a otherwise working custom.dtb generated with jetson-io. I tried setting the serial@0c290000 section status to okay, which resulted in bootloop and the following error:

[    0.831755] gpiochip_add_data: GPIOs 288..511 (tegra-gpio) failed to register
[    0.831795] gpio-tegra186 2200000.gpio: Could not register gpiochip, -517
[    0.832608] gpiochip_add_data: GPIOs 472..511 (tegra-gpio-aon) failed to register
[    0.832647] gpio-tegra186 c2f0000.gpio: Could not register gpiochip, -517

The full log is attached: custom-boot.log (51.7 KB)

I wonder what I’m doing wrong and whether I need to recompile the kernel. On the other hand, device trees were invented to not need to recompile kernel for reconfiguration, right?

The only related topic I found for not older JetPack versions is How to disable SPI2 and enable UART7. That does unfortunately leave open my issue.
How to enable UART7 (D8, D5) as normal UART like other UART (uartc@C280000) - #50 by williamho is very close, but I cannot get more out of it than I did describe above. The BPMP section doesn’t seem to apply for my case - different hardware.

Thanks for your help!


please perform a whole flash process to update board configuration settings.

you should access Jetson AGX Xavier OEM Product Design Guide for reference,
Jetson AGX Xavier brings five UARTs out to the main connector, check pin description for the details.
you should also check this topic for the changes to disable combined uart on Xavier, Issue in disabling combined UART - #6 by JerryChang

JerryChang, thanks for you hints.

You link to a description about disabling combined UART. I don’t understand how this is related, as I believe combined UART means the sort of UART multiplexing that happens for usb UARTC, but not for UARTG (source). Can you please explain if I am wrong?

I don’t know what to look for in the product design guide. The only information I consider helpful is

SPI2: Routed to PCIe x16 connector on carrier board. Alternately available for general SPI usage or as additional UART interface.

of which the latter is exactly what I am trying to achieve.
I also checked devkit PCB schematics to see that SPI2/UART7 is connected only to PCI-E socket.

You say I should do whole flash. I believe I also tried that, will happily try again. But as I only changed pinmux, what would that change? Isn’t pinmux only set to MB1_BCT?
Device tree I changed on device and loaded with FDT in extlinux.conf, so that doesn’t need flashing.
Anyhow, you propose I do the following?

  • Change pinmux with excel sheet to enable UART7 on SPI2 pins → bootloader/t186ref/BCT/tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg
  • Do full flash. ./ jetson-agx-xavier-devkit mmcblk0p1
  • Copy /boot/dtb/.dtb* to custom.dtb and set serial@c290000 to okay
  • Enable custom.dtb as FDT in extlinux.conf


it’s board configuration file changes, SPI2 and UART7 are share pins on module.
so, after configure pinmux, you’ll need to perform a complete flash to have the update correctly.
please also access Xavier TRM, and check [ AO PAD Control Registers] for the register settings.
please check PADCTL_AO_SPI2_MISO_0, PADCTL_AO_SPI2_SCK_0…etc for details.
for example, How to disable SPI2 and enable UART7 - #3 by JerryChang.


I downloaded a fresh BSP/rootfs and changed the following lines in bootloader/t186ref/BCT/tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg:

pinmux.0x0c302048 = 0x00000425; # spi2_sck_pcc0: uartg, pull-down, tristate-disable, input-disable, io_high_voltage-enable, lpdr-disable
pinmux.0x0c302050 = 0x00000475; # spi2_miso_pcc1: uartg, pull-down, tristate-enable, input-enable, io_high_voltage-enable, lpdr-disable
pinmux.0x0c302028 = 0x00000425; # spi2_mosi_pcc2: uartg, pull-down, tristate-disable, input-disable, io_high_voltage-enable, lpdr-disable
pinmux.0x0c302038 = 0x00000475; # spi2_cs0_pcc3: uartg, pull-down, tristate-enable, input-enable, io_high_voltage-enable, lpdr-disable

Then, I did a full flash to AGX: sudo ./ jetson-agx-xavier-devkit mmcblk0p1

The readout of dtc -I fs -O dts /proc/device-tree has disabled status for serial@c290000.
dmesg | grep UART doesn’t list c290000.

So I took the dtb file from /boot/dtb and, with dtc, modified the serial@c290000 section to have okay as status:

	serial@c290000 {
		clock-names = "serial", "parent";
		clocks = <0x4 0xa1 0x4 0x66>;
		compatible = "nvidia,tegra186-hsuart";
		dma-names = "rx", "tx";
		dmas = <0x20 0x2 0x20 0x2>;
		interrupts = <0x0 0x76 0x4>;
		iommus = <0x2 0x20>;
		linux,phandle = <0x166>;
		nvidia,memory-clients = <0xe>;
		phandle = <0x166>;
		reg = <0x0 0xc290000 0x0 0x10000>;
		reg-shift = <0x2>;
		reset-names = "serial";
		resets = <0x5 0x6a>;
		status = "okay";

Having it as FDT entry and booting up gives the same bootloop that I described in the first post.
So my question persists: Apart from configuring pinmux, what do I need to do to enable UARTG?


please share kernel initial messages for reference,


you mean the boot log? I have attached one in the top post. Now I had the same issues with
gpiochip_add_data: GPIOs 288..511 (tegra-gpio) failed to register


tegra186 is for Jetson TX2 series.
please review your driver implementation, at least Jetson AGX Xavier is using tegra194-gpio.

Hello and thanks

that is indeed interesting. So L4T loads gpio-tegra186 when serial@c290000 is set to okay.

After having pinmux configured, what else could I do to get a /dev/ttyTHS7 device?


please attach full initial logs for reference, i.e. bootloader logs and kernel init messages.


for reference, I redid the whole process and added log files, config files or screenlogs everywhere.

Clean start, extract BSP and rootfs from downloaded archives. Run apply_binaries. extract.log (8.7 KB)

Modify Pinmux spreadsheet to enable uartg

The only file changed is tegra19x-jetson_agx_devkit-pinmux.dtsi: pinmux.diff (2.0 KB)

Generated cfg file with

python "$PINMUX_DIR/" \                                         
   --pinmux "$PINMUX_DIR/addr_info.txt" "$PINMUX_DIR/gpio_addr_info.txt" "$PINMUX_DIR/por_val.txt" \
   --mandatory_pinmux_file "$PINMUX_DIR/mandatory_pinmux.txt" \                 
   tegra19x-jetson_agx_devkit-pinmux.dtsi \                                     
   tegra19x-jetson_agx_devkit-gpio-default.dtsi \                               

errors: makecfg.log (2.5 KB)
file: tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg (29.7 KB)
diff: cfg.diff (1.7 KB)

Put file to Linux_for_Tegra/bootloader/t186ref/BCT/tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg

Serial console log for all the rest: boot1-3.log (68.6 KB)

Full flash of AGX Xavier. flash.log (60.0 KB)

Configured via ttyACM, reboot.

Search for uart7 device fails:

  • dmesg | grep -i uart lists only ttyTHS{0, 1, 4}

  • ls /dev/ttyTHS* lists only ttyTHS{0, 1, 4}

  • dtc -I fs -s -O dts /sys/firmware/devicetree/base > sys.dts (359.8 KB) lists serial@c290000 as disabled

  • /sys/kernel/debug/tegra_pinctrl_reg looks alright, uartg selected as pm:
    Bank: 1 Reg: 0x0c302028 Val: 0x00000421 → spi2_mosi_pcc2
    Bank: 1 Reg: 0x0c302038 Val: 0x00000475 → spi2_cs0_pcc3
    Bank: 1 Reg: 0x0c302048 Val: 0x00000421 → spi2_sck_pcc0
    Bank: 1 Reg: 0x0c302050 Val: 0x00000479 → spi2_miso_pcc1

  • journalctl -b attached: journal (294.9 KB)

To be clear: I want a device ttyTHS6 to appear for UARTG and use it to communicate via serial@c290000.

Hello philip,
You should make it “okay”, why your dts saying disabled?
Can you read from /proc/device-tree/serial@c290000/status

shgarg, thanks for your input.

$ cat /proc/device-tree/serial@c290000/status

In the past (see top posts) I did make serial@c290000 okay, but nobody ever confirmed it was necessary or if I did it correctly and it resulted in boot loop. That’s why I didn’t do it last time.

Can you please explain to me what I need to do to make it okay? The obvious way still fails:

Directly after what I did in AGX Xavier enable uartg/uart7 - #12 by philipps, I booted successfully with FDT set to /boot/dtb/kernel_tegra194-p2888-0001-p2822-0000.dtb.
Then, I used dtc to convert this to dts and set serial@c290000/status to okay: custom+uartg.dts (355.9 KB).
Booting from new dtb gives the old bootloop issue. bootloop-uartg.log (31.1 KB). Comparing this log to a successful boot gives following difference:

-Ramdisk: Base: 0x92000000
+Ramdisk: Base: 0x91000000

and errors after bootconsole [tegra_comb_uart0] enabled:

[    0.000000] bootconsole [tegra_comb_uart0] enabled
[    0.850498] gpiochip_add_data: GPIOs 288..511 (tegra-gpio) failed to register
[    0.850542] gpio-tegra186 2200000.gpio: Could not register gpiochip, -517
[    0.851488] gpiochip_add_data: GPIOs 472..511 (tegra-gpio-aon) failed to register
[    0.851529] gpio-tegra186 c2f0000.gpio: Could not register gpiochip, -517
[    1.553374] tegradc 15200000.nvdisplay: failed to parse disp_default_out,-517
[    1.607867] ufs_tegra 2450000.ufshci: ufshcd_get_vreg: vcc get failed, err=-517
[    1.608029] ufs_tegra 2450000.ufshci: Initialization failed
[    1.608284] ufs_tegra 2450000.ufshci: ufshcd_pltfrm_init() failed -517
[    7.055132] ucsi_ccg 1-0008: Setup irq fail, err=-38
[    7.204846] FAN: of_property_read failed
[    7.255131] tegra_aon_mbox_send_data mbox send failed with error -7
[    7.275641] tegra_aon_mbox_send_data mbox send failed with error -7
[    7.275768] tegra186-aondbg aondbg: mbox_send_message failed
[    7.275871] tegra_clocks_config: initialization failed: error -62
[   10.125094] tegra-pcie-dw 141a0000.pcie: DT parsing failed: -517
[   10.164128] ufs_tegra 2450000.ufshci: ufshcd_get_vreg: vcc get failed, err=-517
[   10.164297] ufs_tegra 2450000.ufshci: Initialization failed
[   10.164475] ufs_tegra 2450000.ufshci: ufshcd_pltfrm_init() failed -517
[   10.223282] tegradc 15200000.nvdisplay: dc_hdmi_hotplug_init: couldn't get regulator vdd_hdmi_5v0, -517
[   10.946888] kernel BUG at /dvs/git/dirty/git-master_linux/kernel/nvidia/drivers/platform/tegra/tegra-ivc.c:494!
[   10.947075] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
[   10.947174] Modules linked in:
[   10.947240] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W       4.9.201-tegra #1
[   10.947364] Hardware name: Jetson-AGX (DT)
[   10.947434] task: ffffffc7dc778000 task.stack: ffffffc7dc72c000
[   10.947535] PC is at ivc_write_frame+0x2c0/0x2c8
[   10.947612] LR is at tegra_ivc_write+0x38/0x48
[   10.947685] pc : [<ffffff8008cb5560>] lr : [<ffffff8008cb55a0>] pstate: 808000c5
[   10.947803] sp : ffffffc7dc72fbb0
[   10.947861] x29: ffffffc7dc72fbb0 x28: ffffff8009825478
[   10.947963] x27: ffffff8009669288 x26: ffffff80095ed9b8
[   10.948061] x25: ffffff800a143000 x24: ffffff8009600490
[   10.948511] x23: 0000000000000000 x22: 0000000000000000
[   10.948952] x21: ffffff800fc14080 x20: 0000000000000000
[   10.949403] x19: ffffffc7d7b76298 x18: 0000000000000001
[   10.949833] x17: ffffffbefe847155 x16: 0000000000001400
[   10.951940] x15: 0000000000000000 x14: 0000000000000001
[   10.957881] x13: 000000000000025f x12: ffffffffffffffff
[   10.963481] x11: 000000000000002e x10: 0000000000000007
[   10.969257] x9 : 0000000000000000 x8 : ffffffc7dc72fcc0
[   10.974778] x7 : 0000000000000000 x6 : 00000000331aedaf
[   10.980544] x5 : 00ffffffffffffff x4 : 0000000000000000
[   10.985881] x3 : 0000000000000000 x2 : 0000000000000010
[   10.991220] x1 : ffffff800fc14080 x0 : 0000000000000000
[   10.996556]
[   10.997958] Process swapper/0 (pid: 1, stack limit = 0xffffffc7dc72c000)
[   11.004345] Call trace:
[   11.006711] [<ffffff8008cb5560>] ivc_write_frame+0x2c0/0x2c8
[   11.012047] [<ffffff8008cb55a0>] tegra_ivc_write+0x38/0x48
[   11.016865] [<ffffff8008c9fa74>] tegra_aon_mbox_send_data+0x34/0x88
[   11.022727] [<ffffff8008cb6b10>] msg_submit+0xa8/0x128
[   11.027797] [<ffffff8008cb6eec>] mbox_send_message+0x84/0x158
[   11.032877] [<ffffff8008ca16d0>] aon_create_ivc_dbg_req+0xb0/0x258
[   11.038740] [<ffffff8008ca18b4>] tegra_aon_get_pllaon_state+0x3c/0xa0
[   11.045125] [<ffffff80086a8adc>] clk_aon_is_enabled+0x14/0x20
[   11.050204] [<ffffff8008689c84>] clk_unprepare_unused_subtree+0x64/0x1d0
[   11.056673] [<ffffff800868ad6c>] clk_disable_unused+0x9c/0x138
[   11.062362] [<ffffff8008083b3c>] do_one_initcall+0x44/0x130
[   11.068050] [<ffffff8009600d18>] kernel_init_freeable+0x1a0/0x244
[   11.073916] [<ffffff8008f5ca10>] kernel_init+0x18/0x108
[   11.079335] [<ffffff80080838a0>] ret_from_fork+0x10/0x30
[   11.084855] ---[ end trace 21c3d925dcd41e3d ]---
[   11.096548] note: swapper/0[1] exited with preempt_count 1
[   11.096684] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[   11.096684]
[   11.103843] SMP: stopping secondary CPUs
[   11.107786] Kernel Offset: disabled
[   11.111621] Memory Limit: none
[   11.114512] trusty-log panic notifier - trusty version Built: 08:40:57 Feb 19 2021 [   11.129659] Rebooting in 5 seconds..


Luckily, I got a hint by another forum user. I managed to get an uartg device by

  • downloading the kernel sources with -k tegra-l4t-r32.5.1
  • inserting into hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0000-a00.dtsi
	serial@c290000 {
		compatible = "nvidia,tegra186-hsuart";
		status = "okay";

What I still don’t understand is why stock kernel doesn’t support enabling of serial@c290000 device.