Please refer to design files, schematic and layout files in package to find out the pins: [url]http://developer.nvidia.com/embedded/dlc/jetson-xavier-developer-kit-carrier-board-design-files-b03[/url]
Also please don’t file two topics for same one question. Thanks.
Yes, thank you for pointing out!
And there are linked threads:
It seems that UART5[j58&h58] are somehow utilized by M.2 E.
Does that mean if I have the M.2 E slot non occupied at the devkit I could just find corresponding pins somewhere and wire to them?
Yes, you can find the pins on the slot.
IS there a way to get the pins to J30 interface somehow ?
Trigger somehow them internally?
In a way I will have to wire rather to J30 pins than to M.2 E slot that has micro format?
Could you help determining the suitable pins of the J30 interface, please?
I am not to post to other threads , I just had to ask the engineer guy at another thread as he started explaining the idea of how to get it done. Moreover, I as well started a new thread for the clearness, but it wouldn’t help get responses from that guy in the new thread and that is why I had to continue the discussion here and there. Thank you for understanding. :)
It seems that I need to modify device tree somehow for J30 pins to be used as GPS RX and TX. As I understand for that purpose by default M.2 E pins are assigned.
And if I use the M.2 E, Will I just wire to the pins below?
I understand that folks used GPIO assignment somehow for GPS utilization. But that sounds too vague to me.
You can try the pins of J30 if voltage level is same to your GPS device, and so change dts per pinmux sheet.
Thank you for the update.
It seems that I shall find pins with 1-5v parameters, given that I am to use the device
As it is described it will take 5v separately from usb and will need to be wired only by two wires to TX and RX pins.
After checking with the documents, it appears that some random pins of J30 like the below can be approached:
Could you provide insights on modification of the device tree for the purpose, please?
Not sure if 3V3 pin of J30 fit your device as it looks need 5V pin, please ask vendor for that.
Nah, the device will take 5v from usb port [I will cut USB A cable and it will take 5v and ground from it ] directly with two wires of the USB-A cable.However, additionally, it will need to be connected with TX and RX and PPS wires to the xavier J30, as I understand.
Folks describe this rather frequent procedure as:[i]
The Garmin TX, RX and ground data connections go to DB-9 RX, TX and ground connections. It may also be that you find two thin black lines in the Garmin cable once you have removed the test header and stripped the cable back for use in your own system, in which case you can connect both lines to signal ground. If someone spots this, could they please check it both thin blacks are connected so that I can report here?
The Garmin yellow PPS (pulse per second) line is connected to the DB-9 DCD (pin 1). Mine is also connected to a LED via a 3.3K resistor so that there is a visual indication of the PPS signal. I still see over 4V on of the PPS line. Update: the LED was a little dark, so I changed the resistor to 1.5K and replaced the LED with a special low-current (2mA) one from Maplins. Now easily seen in daylight - I await being dazzled at night!
It seems that the GPS 18 has drive capability to support two RS-232 receivers at the same time from the one connection, and I’ve used this to support a second, parallel-connected PC with just Ground, DCD and TX data from the GPS 18 LVC connected.[/i]
Source: An NTP Stratum-1 clock usng a GPS 18 LVC and FreeBSD
They normally seem to wire it to DB-9 connector on a generic workstation.
Synchronizing ntpd to a Garmin GPS 18 LVC via gpsd
Synchronising to a Garmin GPS 18 LVC
However, I shall contact the manufacturer. But what shall I ask them? What information will be required from them to understand how to get it integrated with Xavier via e.g. J30?
Some generic question like “How to get it connected to custom computer with GPIO / I2C” wont help, will it?
And may be you know how to enable at Xavier: “CONFIG_PPS_CLIENT_GPIO”?
Wayne previously mentioned some direction as “K53,K54,L51,H54. (UART1 TX,RX,RTS,CTS)”[url]https://devtalk.nvidia.com/default/topic/1046186/jetson-agx-xavier/connecting-gps-with-pps-to-xavier/post/5309039/#5309039[/url]
but where to find them at the surface? What interface is it? At the surface?
8,10 pins of J30, right? as UART1 TX and RX respectively, and pins 36 as UART1_CTS and pin 11 as UART_RTS ? Right?
And I shall ask in that case the manufacturer if the device will work with 3v3 volts, right?
Please make sure uart5 is already being set as below in pinmux.
pinmux.0x0243d098 = 0x00000400; # uart5_tx_py5: uarte, tristate-disable, input-disable, lpdr-disable pinmux.0x0243d090 = 0x00000458; # uart5_rx_py6: uarte, pull-up, tristate-enable, input-enable, lpdr-disable pinmux.0x0243d0a0 = 0x00000400; # uart5_rts_py7: uarte, tristate-disable, input-disable, lpdr-disable pinmux.0x0243d0a8 = 0x00000458; # uart5_cts_pz0: uarte, pull-up, tristate-enable, input-enable, lpdr-disable
Then, please make sure the Device tree is set to enabled.
nvidia@nvidia-desktop:/proc/device-tree/serial@3140000$ xxd status 00000000: 6f6b 6179 00 okay.
By default, this should be all enabled on devkit.
the latter I can do:
nvidia@nvidia-desktop:/proc/device-tree/serial@3140000$ xxd status 00000000: 6f6b 6179 00
And how do I check the former?
/proc/device-tree/pinmux@2430000$ ls '#gpio-range-cells' i2s1_dap_active phandle clkreq_c5_bi_dir i2s2_dap_active reg compatible i2s3_dap_active status dmic1_dap_active i2s4_dap_active vbus_en0_default dmic2_dap_active i2s5_dap_active vbus_en0_oc_passthrough dmic3_dap_active i2s6_dap_active vbus_en0_oc_tristate dmic3_dap_inactive linux,phandle vbus_en1_default dmic4_dap_active name vbus_en1_oc_passthrough dspk0_dap_active pex_rst_c5_in vbus_en1_oc_tristate dspk1_dap_active pex_rst_c5_out
The former one is a file inside Linux_for_Tegra/bootloader. You could just grep the keyword and the file shall be shown.
Thank you for your response.
At Xavier I can see:
/sys/kernel/debug/pinctrl/2430000.pinmux# ls gpio-ranges pinconf-groups pinconf-pins pinmux-functions pins pinconf-config pinconf-pin-prop pingroups pinmux-pins
I can not observe the folder “Linux_for_Tegra/bootloader” neither at Host PC, nor at the Xavier. However, at the latter I can see folders :
nvidia@nvidia-desktop:~$ locate bootloader /usr/sbin/nv_bootloader_payload_updater /usr/src/linux-headers-4.15.0-47/arch/alpha/boot/bootloader.lds /usr/src/linux-headers-4.15.0-47/arch/ia64/hp/sim/boot/bootloader.lds /usr/src/linux-headers-4.15.0-47-generic/include/config/efi/bootloader /usr/src/linux-headers-4.15.0-47-generic/include/config/efi/bootloader/control.h /usr/src/linux-headers-4.9.140-tegra-linux_x86_64/kernel-4.9/arch/alpha/boot/bootloader.lds /usr/src/linux-headers-4.9.140-tegra-linux_x86_64/kernel-4.9/arch/ia64/hp/sim/boot/bootloader.lds /usr/src/linux-headers-4.9.140-tegra-ubuntu18.04_aarch64/kernel-4.9/arch/alpha/boot/bootloader.lds /usr/src/linux-headers-4.9.140-tegra-ubuntu18.04_aarch64/kernel-4.9/arch/ia64/hp/sim/boot/bootloader.lds
As far as I remember the Linux_for_Tegra folder was created while using Jetpack installation method at Host PC. Does it need to be checked at Host PC? Before re-flashing Jetson? Will reflashing be required?