How to enable AGX Xavier devkit SPI1 on spe-fw?


In the official SPI demo for spe-fw, SPI2 is used. However SPI2 is hidden in PCIe x16 connector (J6) of AGX Xavier devkit. We can’t find a convenient and reliable method to connect it. So we want to enable SPI1 based on the official SPI2 demo. The L4T verison is r32.7.3 and SPE is r32.6.1. But we encountered some issues when we flashed the firmware. We modified relevant file from both Linux kernel and spe-fw side.

We compiled the spe-fw without any error or warning, then rename to spe_t194.bin and copy to Linux_for_Tegra/bootloader/

We made sure the board in Force Recovery Mode before flash. For Xavier, we saw 7019 after running lsusb . Then the board was flashed by the following command:

sudo ./ jetson-xavier mmcblk0p1

Then the following error occurred:

[   8.0278 ] Sending bootloader and pre-requisite binaries
[   8.0304 ] tegrarcm_v2 --download blob blob.bin
[   8.0320 ] Applet version 01.00.0000
[   8.1061 ] Sending blob
[   8.1064 ] [................................................] 100%
[   8.9149 ] 
[   8.9194 ] tegrarcm_v2 --boot recovery
[   8.9210 ] Applet version 01.00.0000
[   8.9985 ] 
[  10.0041 ] tegrarcm_v2 --isapplet
[  10.0067 ] USB communication failed.Check if device is in recovery
[  10.1087 ] 
[  10.1134 ] tegrarcm_v2 --ismb2

The flashing process hangs. This error is similar to this topic. The debug UART may break the flashing process. And if I used the previous spe_t194.bin which enables SPI2 with official demo, it works well. I think there must be something I didn’t modify correctly for SPI1.

In addition, from TRM manual, I find that only SPI2 is the local peripheral of SPE. If I enable SPI1, the DMA channel also could be implemented correctly in function spi_app_init() in ‘l4t-rt/rt-aux-cpu-demo/app/spi-app.c’.

void spi_app_init(void)
	int ret;
	struct tegra_spi_client_setup spi_test_device[] = {
			.chip_select = 0,
			.set_rx_tap_delay = false,
			.spi_max_clk_rate = SPI_TEST_CLOCK_RATE,
			.spi_no_dma = false,
	struct tegra_spi_master_init master_test_conf[] = {
			.dma_id = &tegra_gpcdma_id_aon,
			.dma_channel.tx = SPI_TEST_DMA_TX_CHANNEL,
			.dma_channel.rx = SPI_TEST_DMA_RX_CHANNEL,
			.spi_max_clk_rate = SPI_TEST_CLOCK_RATE,
			.dma_slave_req = GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_SPI,

I think all of values about DMA must be modified. But I don’t find any demo for it. Maybe, for SPI1, only IPO mode can be used? or maybe SPI1 can not be used in spe-fw?

I need your help to give me some advises about how to enable SPI1 on spe-fw.

Could you verify the spe_t194.bin without any modify to check if able to flash ?


Of course, I do verify the spe_t194.bin can be flashed and run correctly only with modification in
In addition, with ENABLE_SPI_APP = 1,the spe_t194.bin can also be flashed. But I can’t short MISO and MOSI signals of SPI2, so printf Received incorrect data debug info in combined UART.

@ShaneCCC @jachen I need your help.

Hello, Xu_Xu:
What’s the problem you met?
I’m a little confused why ‘But I can’t short MISO and MOSI signals of SPI2,’.

Generally, you can debug the issue step by step.

  1. Follow the SPI doc, add some print debug code in SPE firmware, update/compile, …, and re-flash the device
  2. When the SPE FW in device is updated, take a look at console log and make sure the SPI app is running.
  3. Check signal in SPI pins, and check whether it’s expected.
    3.1 If no toggle of pins when SPI tx routine is called, maybe something’s wrong with device settings, like pinmux.
    3.2 If you can see waveforms, basic pin config should be good. Check clock/CS. You can focus on SPI setting then.


Thanks for your reply.

‘But I can’t short MISO and MOSI signals of SPI2,’

Because SPI2 of AGX Xavier devkit is in PCIe x16 connector (J6), I can’t find a way to short them. So I want to enable SPI1 on spe-fw.
For this purpose, I have modified the code to enable SPI1 based on official SPI2 example. But I can’t enable agx xavier based on the modified code. In addition, from TRM manual, I find that only SPI2 is the local peripheral of SPE. If I enable SPI1, could the DMA channel also be implemented correctly in function spi_app_init() in ‘l4t-rt/rt-aux-cpu-demo/app/spi-app.c’. ? I think this part of code about DMA may be the root cause of the problem. I want you to confirm whether this is the problem.

Please note that only modules in AON cluster can be accessed by SPE FW.
SPI1 is not supported in SPE FW.

You may have to re-design the carrier board, or wire-out corresponding SPI2 pins for that test.



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