How to enable ECC support on TX2i?

Hi. I am developing CUDA programms on one Jetson Tx2i module. It is said by the document Jetson_TX2_TX2i_Module_DataSheet_v1.1 that DRAM ECC (enabled by software for TX2i only). I want to know how to enable ECC support by software? Is there any command or API? I’m looking forward to the answers. Thank you!

hello Lee1980,

A57 ECC is enabled by default, Denver ECC it is always enabled and it is not configurable.

Thank you for your answers. And there are more questions about ECC. Based on the Jetson_TX2_TX2i_Module_DataSheet_v1.1, it says that “128-bit Memory Controller.128-bit DRAM interface providing high bandwidth LPDDR4 and ECC (TX2i only) support”. I wonder whether the ECC function takes effect when exchanging data between the CPUs and GPU by the DRAM inside of TX2i. When GPU threads access page-locked or PINNED Memory, does ECC function also take effect?

When I run deviceQuery on TX2i, it prints the following messeges. I think the GPU device of TX2i is the same as TX2 (Device has ECC support: Disabled). The GPU device of TX2i has no ECC function support (I mean there is no ECC on global memory). Is it right?

And is there any command to disable A57 ECC?

./deviceQuery Starting…

CUDA Device Query (Runtime API) version (CUDART static linking)

Detected 1 CUDA Capable device(s)

Device 0: “NVIDIA Tegra X2”
CUDA Driver Version / Runtime Version 9.0 / 9.0
CUDA Capability Major/Minor version number: 6.2
Total amount of global memory: 6838 MBytes (7170465792 bytes)
( 2) Multiprocessors, (128) CUDA Cores/MP: 256 CUDA Cores
GPU Max Clock rate: 1237 MHz (1.24 GHz)
Memory Clock rate: 1600 Mhz
Memory Bus Width: 128-bit
L2 Cache Size: 524288 bytes
Maximum Texture Dimension Size (x,y,z) 1D=(131072), 2D=(131072, 65536), 3D=(16384, 16384, 16384)
Maximum Layered 1D Texture Size, (num) layers 1D=(32768), 2048 layers
Maximum Layered 2D Texture Size, (num) layers 2D=(32768, 32768), 2048 layers
Total amount of constant memory: 65536 bytes
Total amount of shared memory per block: 49152 bytes
Total number of registers available per block: 32768
Warp size: 32
Maximum number of threads per multiprocessor: 2048
Maximum number of threads per block: 1024
Max dimension size of a thread block (x,y,z): (1024, 1024, 64)
Max dimension size of a grid size (x,y,z): (2147483647, 65535, 65535)
Maximum memory pitch: 2147483647 bytes
Texture alignment: 512 bytes
Concurrent copy and kernel execution: Yes with 1 copy engine(s)
Run time limit on kernels: No
Integrated GPU sharing Host Memory: Yes
Support host page-locked memory mapping: Yes
Alignment requirement for Surfaces: Yes
Device has ECC support: Disabled
Device supports Unified Addressing (UVA): Yes
Supports Cooperative Kernel Launch: Yes
Supports MultiDevice Co-op Kernel Launch: Yes
Device PCI Domain ID / Bus ID / location ID: 0 / 0 / 0
Compute Mode:
< Default (multiple host threads can use ::cudaSetDevice() with device simultaneously) >

deviceQuery, CUDA Driver = CUDART, CUDA Driver Version = 9.0, CUDA Runtime Version = 9.0, NumDevs = 1
Result = PASS

hello Lee1980,

we had some related topics discussed this before, you may also check Topic 1000685 for reference.