Is LPDDR4 ECC enabled by default on Jetson TX2i? How can I check for corrected or detected bits? Is Edac available in the kernel?


Yes LPDDR4 ECC is enabled by default on Jetson TX2i.
The ECC events are not handled by kernel, they are handled by a firmware running on SCE core in the SoC.
Kernel DT has a field to control if the ECC events should generate kernel interrupt in the path

mc {

Absence of this property causes ECC events to be handled in kernel. When the event occurs, kernel will print the summary of the error.
But irrespective of the above configuration, SCE firmware will continue to handle the events. So it is discouraged to handle the events in kernel.

Hi vishruthj,
Thank you for your quick answer.
I searched information about the kernel property ecc_on_camera_fw, and it seems to me that the error is handled by the SCE Core, since dmesg returns me this info:

dram-ecc: SCE-R5 is booted with Camera FW

Just to understand a little bit more, what is this firmware doing? Is it launched by a kernel module? Where can I find information about it?
I’m a little worried because it’s seems to be related to the camera subsystem, but i’m not actually using any camera.


The camera firmware has dual functionality of handling camera function and the DRAM ECC function.
It is an independent firmware loaded by bootloader. It is not initialized by kernel.