How to enable UART5 properly

Robotics & Edge Computing Jetson & Embedded Systems Jetson AGX Orin
1

We use AGX Xavier module with our custom carrier board with Jetpack 4 today, and are trying to see if we can upgrade to AGX Orin module with the same custom carrier board running Jetpack 6. After a couple of weeks effort, we are able to bring up the system. During our full testing, we notice one issue with UART. When we use AGX Xavier with our customer board, UART1 connects to first STM32 MCU on the custom carrier board, and UART2 connects to the second STM32 MCU. Both have communication working fine. When migrating to AGX Orin, UART1 keeps working, but UART2 fails. Further investigation shows Orin changed the pin number for UART2. The old UART2 TX/RX (Pin C58/C56) now becomes UART5 TX/RX. We enabled UART5 in the device tree, but the communication still failing with second STM32.

                serial@3140000 {
                        compatible = "nvidia,tegra194-hsuart";
                        reg = <0x00 0x3140000 0x00 0x10000>;
                        interrupts = <0x00 0x74 0x04>;
                        clocks = <0x03 0x9f>;
                        resets = <0x03 0x68>;
                        dmas = <0xee 0x14 0xee 0x14>;
                        dma-names = "rx\0tx";
                        status = "okay";
                        reset-names = "serial";
                        phandle = <0x22e>;
                };

Here is the pinmux.dtsi (I didn’t manually edit this file), generated from AGX Orin pinmux sheet:

                        uart5_tx_py5 {
                                nvidia,pins = "uart5_tx_py5";
                                nvidia,function = "uarti";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };

                        uart5_rx_py6 {
                                nvidia,pins = "uart5_rx_py6";
                                nvidia,function = "uarti";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };
                        uart5_rts_py7 {
                                nvidia,pins = "uart5_rts_py7";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };

                        uart5_cts_pz0 {
                                nvidia,pins = "uart5_cts_pz0";
                                nvidia,function = "rsvd1";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };

In our hardware wiring, we only use TX/RX, there is no flow control.

Here is the dmesg output:

nvidia@localhost:~$ sudo dmesg | grep -i serial
[    0.130776] Serial: AMBA PL011 UART driver
[    0.142379] 31d0000.serial: ttyAMA0 at MMIO 0x31d0000 (irq = 119, base_baud = 0) is a SBSA
[    0.273584] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    0.275738] msm_serial: driver initialized
[    5.144207] serial-tegra 3100000.serial: RX in PIO mode
[    5.144213] serial-tegra 3100000.serial: TX in PIO mode
[    5.144345] 3100000.serial: ttyTHS1 at MMIO 0x3100000 (irq = 112, base_baud = 0) is a TEGRA_UART
[    5.145408] 3140000.serial: ttyTHS4 at MMIO 0x3140000 (irq = 113, base_baud = 0) is a TEGRA_UART
[    5.146225] serial-tegra 3110000.serial: RX in PIO mode
[    5.146229] serial-tegra 3110000.serial: TX in PIO mode
[    5.146251] 3110000.serial: ttyTHS2 at MMIO 0x3110000 (irq = 205, base_baud = 0) is a TEGRA_UART
[    9.767131] systemd[1]: Created slice Slice /system/serial-getty.
nvidia@localhost:~$ sudo cat /sys/kernel/debug/pinctrl/2430000.pinmux/pinconf-groups | grep uart
88 (uart2_tx_px4): 
	function=uartb
89 (uart2_rx_px5): 
	function=uartb
90 (uart2_rts_px6): 
	function=uartb
91 (uart2_cts_px7): 
	function=uartb
92 (uart5_tx_py5): 
93 (uart5_rx_py6): 
94 (uart5_rts_py7): 
95 (uart5_cts_pz0): 
120 (uart1_cts_pr5): 
	function=uarta
121 (uart1_rts_pr4): 
	function=uarta
122 (uart1_rx_pr3): 
	function=uarta
123 (uart1_tx_pr2): 
	function=uarta
125 (uart4_cts_ph6): 
126 (uart4_rts_ph5): 
127 (uart4_rx_ph4): 
128 (uart4_tx_ph3):

We tried to read the hardware registers

#TX register
nvidia@localhost:~$ sudo busybox devmem 0x024340b0 32                              
0x00000400
#RX register
nvidia@localhost:~$ sudo busybox devmem 0x024340b8 32
0xFFFFFFFF

The 0xFFFFFFFF from RX register looks suspicious. When we read it, it prints below errors on the console:

[  685.916316] CPU:0, Error: cbb-fabric@0x13a00000, irq=182    
[  685.916337] **************************************                           
[  685.916339] CPU:0, Error:cbb-fabric, Errmon:2                                
[  685.916347]    Error Code            : SLAVE_ERR                             
[  685.916357]                                                                  
[  685.916360]    Error Code            : SLAVE_ERR                             
[  685.916362]    MASTER_ID             : CCPLEX                                
[  685.916365]    Address               : 0x24340b8                             
[  685.916367]    Cache                 : 0x0 -- Device Non-Bufferable          
[  685.916371]    Protection            : 0x2 -- Unprivileged, Non-Secure, Data 
Access                                                                          
[  685.916376]    Access_Type           : Read                                  
[  685.916378]    Access_ID             : 0x16                                  
[  685.916380]    Fabric                : cbb-fabric                            
[  685.916383]    Slave_Id              : 0x35                                  
[  685.916385]    Burst_length          : 0x0                                   
[  685.916387]    Burst_type            : 0x1                                   
[  685.916389]    Beat_size             : 0x2                                   
[  685.916391]    VQC                   : 0x0                                   
[  685.916393]    GRPSEC                : 0x7e                                  
[  685.916395]    FALCONSEC             : 0x0                                   
[  685.916398]    Slave                 : AXI2APB_35                            
[  685.916402]  **************************************                          
[  685.916445] WARNING: CPU: 0 PID: 0 at drivers/soc/tegra/cbb/tegra234-cbb.c:60
8 tegra234_cbb_isr+0x14c/0x180                                                  
[  685.916903] ---[ end trace 1dc5b9d1214f72ca ]---

How can we properly enable UART5, so that our old UART2 wiring can work?

2

*** Please note that this reply is generated by LLM automatically ***

To properly enable UART5 on the Jetson AGX Orin module, you need to make sure that the pinmux configuration is correct and that the device tree is updated to reflect the changes.

Firstly, let’s compare the pinmux configuration for UART2 on the Jetson AGX Xavier module and UART5 on the Jetson AGX Orin module.

On the Jetson AGX Xavier module, UART2 is connected to pins C58 and C56. However, on the Jetson AGX Orin module, UART5 is connected to the same pins. This means that you need to update your device tree to reflect this change.

To enable UART5 on the Jetson AGX Orin module, you need to add the following lines to your device tree:

&uart5 {
    status = "okay";
    nvidia,enable-hw-flow-control;
};

You also need to update the pinmux configuration to reflect the changes. You can do this by adding the following lines to your pinmux configuration file:

pinmux.0x0c303000 = 0x00000400; /* uart5_tx */
pinmux.0x0c303008 = 0x00000400; /* uart5_rx */

Make sure to update the pinmux configuration file to reflect the correct pin numbers for UART5.

Once you have updated the device tree and pinmux configuration, you should be able to enable UART5 on the Jetson AGX Orin module.

Regarding the error messages you are seeing, the 0xFFFFFFFF value in the RX register is likely due to the fact that the UART5 receiver is not enabled. To enable the UART5 receiver, you need to set the nvidia,enable-hw-flow-control property in the device tree.

Additionally, you may need to update your hardware wiring to reflect the changes in the pinmux configuration. Make sure that the TX and RX pins are connected to the correct pins on the Jetson AGX Orin module.

In comparison to the Jetson AGX Xavier module, the Jetson AGX Orin module has a different pinmux configuration for UART5. On the Jetson AGX Xavier module, UART2 is connected to pins C58 and C56, whereas on the Jetson AGX Orin module, UART5 is connected to the same pins. This means that you need to update your device tree and pinmux configuration to reflect the changes.

In summary, to properly enable UART5 on the Jetson AGX Orin module, you need to:

  1. Update the device tree to reflect the changes in the pinmux configuration.
  2. Update the pinmux configuration to reflect the correct pin numbers for UART5.
  3. Enable the UART5 receiver by setting the nvidia,enable-hw-flow-control property in the device tree.
  4. Update your hardware wiring to reflect the changes in the pinmux configuration.

By following these steps, you should be able to enable UART5 on the Jetson AGX Orin module and resolve the issues you are seeing.

*** Please give the thumbs up if you get answers you like. Or provide feedback to help us improve the answer. ***

3

Those pinmux.cfg is no longer used in Orin / Jetpack 6. We use the dtsi files generated by pinmux spreadsheet directly. Do you see any issues with the uart5 section in my dtsi file that I posted above?

4

Does the 0xFFFFFFFF from the RX register means some access denied or hardware lo
ckout? Is that because SPE claimed it for debug port? I checked the default file
Linux_for_Tegra/bootloader/tegra234-mb2-bct-common.dtsi and find:

        enable_combined_uart = <1>;
        spe_uart_instance = <2>;

Does <2> in spe_uart_instance mean it locks our UART5 for the combined_uart?

6

Based on the generated pinmux dtsi, the UART5 has:

nvidia,function = "uarti";

For uarti, am I enabling the correct one (serial@3140000) in my dts? If 3140000 is not the right one for uarti, which address shall I use to enable?

7

Decompiled kernel dtb file shows uarti as

                serial@31d0000 {
                        compatible = "arm,sbsa-uart";
                        reg = <0x00 0x31d0000 0x00 0x10000>;
                        interrupts = <0x00 0x11d 0x04>;
                        status = "okay";
                        current-speed = <0x1c200>;
                        phandle = <0x232>;
                };

Does that mean there are some sort of conflict between my old Xavier UART2, and now the new Orin 31d0000 (sbsa-uart)?

8

Ok, I am trying to add uarti for my usage:

                serial@31d0000 {
                        compatible = "nvidia,tegra194-hsuart";
                        reg = <0x00 0x31d0000 0x00 0x10000>;
                        interrupts = <0x00 0x11d 0x04>;
                        status = "okay";
                        clocks = <0x03 0xa3>;
                        resets = <0x03 0x77>;
                        reset-names = "serial";
                        phandle = <0x232>;
                }

But now the system won’t boot anymore, with error:

ERROR:   Exception reason=0 syndrome=0xbe000411                             

ERROR:   **************************************                                 

ERROR:   RAS Uncorrectable Error in IOB, base=0xe010000:                        

ERROR:          Status = 0xec000612                                             

ERROR:   SERR = Error response from slave: 0x12                                 

ERROR:          IERR = CBB Interface Error: 0x6                                 

ERROR:          Overflow (there may be more errors) - Uncorrectable             

ERROR:          MISC0 = 0xc45e0040                                              

ERROR:          MISC1 = 0x24c860000000000                                       

ERROR:          MISC2 = 0x0                                                     

ERROR:          MISC3 = 0x0                                                     

ERROR:          ADDR = 0x80000000031d000c                                       

ERROR:   **************************************                                 

ERROR:   sdei_dispatch_event returned -1                                        

ERROR:   **************************************                                 

ERROR:   RAS Uncorrectable Error in ACI, base=0xe01a000:                        

ERROR:          Status = 0xe8000904                                             

ERROR:   SERR = Assertion failure: 0x4                                          

ERROR:          IERR = FillWrite Error: 0x9                                     

ERROR:          Overflow (there may be more errors) - Uncorrectable             

ERROR:          ADDR = 0x80000000031d000c                                       

ERROR:   **************************************                                 

ERROR:   sdei_dispatch_event returned -1                                        

ERROR:   Powering off core
9

Hi user100132,

What’s the exact Jetpack version in use?
Please share the result of cat /etc/nv_tegra_release on your board.

Please configure them as uarte instead from pinmux spreadsheet as following:
image

You can also refer to the following link for the UART mapping.
https://elinux.org/Jetson/L4T/peripheral/#Mapping_3

10

Thanks @KevinFFF I didn’t realize UART5 can be configured for either uarti (default) or uarte.

11

Yes, this interface is pinmuxed for uart-e and uart-i.
If you want to use it as normal UART, please configure it as UART-E(3140000.serial).
UART-I(31d0000.serial) is used when it is used for the secondary debug UART(SBSA UART).

1 Like
12

Can UPHY pins be pinmux too? The pins for USB uphy seems to have changed too, from Xavier to Orin. Our usb ports become usb 2.0 only.

13

You may refer to Jetson AGX Orin Series and Jetson AGX Xavier Series Interface Comparison and Migration Application Note from Jetson Download Center for details.
For the interface other than UART, please create another topic to discuss.