By default the aud_mclk is configured to be 256 * fs. So if your sample-rate is 44.1kHz, then the aud_mclk will be ~11.2896MHz. The bit clock is configured to be sample-rate * sample-size * number of channels.
The datasheet for SPH0645LM4H microphone featured on the I2S MEMs card states …
“The SPH0645LM4H microphone operates as an I2S
slave. The master must provide the BCLK and WS
signals. The Over Sampling Rate is fixed at 64 therefore
the WS signal must be BCLK/64 and synchronized
to the BCLK. Clock frequencies from 2.048Mhz to
4.096MHz are supported so sampling rates from 32KHz
to 64KHz can be had by changing the clock frequency.”
So I am not sure you can support a clock as low as 1.024MHz and it needs to be in the range from 2.048MHz to 4.096MHz.
The easiest way to reduce the bit clock is to reduce the sampling rate. For example, if you use a sample rate of 32kHz, then the bit clock should be 2.048MHz (32000 * 32 * 2).
If you are using the ‘arecord’ command to capture audio, then you can use the ‘-r’ option to set the sample rate to 32000Hz.