I2S Master Clock (MCLK) Low Amplitude Signal

The I2S Master Clock being generated by Xavier (at GPIO09, pin 211 as AUD_MCLK) is being produced at an extremely low voltage range (cycling between 1.6 and 1.7 Volts). The frequency is configurable/controllable and being properly produced – but the expected 0V to 1.8V range for the clock is not seen.

Additional Context:
When the pin is configured as GPIO and toggled at lower frequencies, the proper 0-1.8V range is seen. So the issue does not appear to be an electrical / board level issue with this signal path.

Can anyone provide insight into what we are seeing here / how we can resolve this issue?

May I have your comment for this topic.


Hi mwood,

How are you configuring the pinmux for the I2S pins. Is it via Jetson-IO tool or from pinmux xls sheet?

If not doing already via Jetson-IO. Please configure 40 pin header’s I2S pinmux via Jetson IO and share the settings (via cat /sys/kernel/debug/pinctrl/2430000.pinmux/pinconf-groups)


Issue resolved :
The attenuated signal was the result of a low bandwidth measurement device (measurement error). The logic analyzer being used to probe this 12.5 MHz signal did not have sufficient bandwidth to accurately display the clock. When reverified with a 100MHz O-scope, the signal was confirmed as expected (3.3V logic level).

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