How to use UART port in jetson TX2?

How to transmit and receive data through the uart pins. I want to connect the FPGA through UART pins and make communication in between.


This forum is for community feedback. I will move this to the Jetson TX2 forum for you.

UARTs are not generally used for high speed data, but are quite good at lower speeds. Assuming this is the NVIDIA devel carrier board, then serial UARTs use a 3.6V TTL logic level, and if your FPGA uses the same logic level, then you can directly wire together (left/right side representing TX2/FPGA):

# If you use flow control, then also:

In terms of files for access, the naming is such that a “/dev/ttyS#” file and a “/dev/ttyTHS#” file (where “#” is the same 0…N) are the same hardware, but different drivers. Serial console uses the old “/dev/ttyS0”, which is the same hardware as “/dev/ttyTHS0”. The reason serial console uses the ttyS0 driver instead of ttyTHS0 is because U-Boot needs to hand off to the kernel during boot without resetting the UART, and U-Boot does not understand the ttyTHS drivers (ttyS is older, ttyTHS uses DMA). Basically you are interested in anything from “ls /dev/ttyTHS*” other than “/dev/ttyTHS0”…provided the UART is exposed on a header. The dev kit J17 header is unused and should be considered your simplest test case (which is “/dev/ttyTHS2”).

UARTs are accessed as regular files, although extended control exists through IOCTL calls. The ports at both ends of the connection must have the same settings. If settings differ, then either you won’t get any traffic, or the traffic will be corrupt.

To demonstrate this you can use loopback. Loopback tests are great because no serial port will disagree with itself on the current settings. If you were to install gtkterm (“sudo apt-get install gtkterm”…or use some other serial terminal), then jumper J17 TX to RX (and its own CTS to its own RTS if using flow control), then this would bring up a terminal where typing in gets echoed back:

sudo gtkterm -b 8 -t 1 -s 115200 -p /dev/ttyTHS2

That is for speed 115200, 8 bits, one stop bit, no parity. If you want to go higher than 115200, then you would probably want to switch to two stop bits. The serial terminal is able to provide the needed IOCTL calls. Whatever you think you are going to use as a setting on the FPGA just test with loopback first at those settings on a local terminal. Hardware flow control may be useful as the speed goes up, but you can test without it first.

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