How to use Xavier PCIe interconnection

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
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1

Hello,
We want to bringup the xavier PCIe interconnection.
The hardware design is as follows:

  1. master NVHS_TX <<==>> slave NVHS_SLVS_RX(x8)
  2. master PEX_CLK5 <<==>> slave NVHS0_SLVS_REFCLK0
  3. master PEX_L5_RST_N <<==>> slave PEX_L5_RST_N
  4. master PEX_L5_CLKREQ_N <<==>> PEX_L5_CLKREQ_N
  5. master NVHS_SLVS_RX <<==>> slave NVHS_TX(x8)
    Question:
    How to use this, and test it.
    The hardware design is correct?
3

For the PCIe design between two Xavier, please refer to the application note in DLC and also the Xavier Design Guide.

https://developer.nvidia.com/embedded/dlc/jetson-agx-xavier-series-pcie-endpoint-design-guidelines-application-note

https://developer.nvidia.com/embedded/dlc/jetson-agx-xavier-series-oem-product-design-guide

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