We want to bringup the xavier PCIe interconnection.
The hardware design is as follows:
- master NVHS_TX <<==>> slave NVHS_SLVS_RX(x8)
- master PEX_CLK5 <<==>> slave NVHS0_SLVS_REFCLK0
- master PEX_L5_RST_N <<==>> slave PEX_L5_RST_N
- master PEX_L5_CLKREQ_N <<==>> PEX_L5_CLKREQ_N
- master NVHS_SLVS_RX <<==>> slave NVHS_TX(x8)
How to use this, and test it.
The hardware design is correct?