HW accelerated encoding

I have a general question, does the H264/265, VP9/8 HW accelerated encoders are part of the Tegra X2 SoC? I couldn’t find any references to that subject in the TRM.

It should be referred as NVENC.
It should support H264 and H265.
For recent L4T versions, VP9 should be available.
For VP8, I don’t know for TX2, it was available for Xavier in some old versions but has been removed a few releases ago.

Thank you, is NVENC in the Tegra SoC or GPU?

It is in the SoC, along with the decoder. Neither uses GPU resources for encode/decode. You can find the detailed specs on the codecs/resolutions/rates they support in the module datasheets.

So this is not NVENC? To use this hw accelerated feature in gstreamer I should use gst-omx elements?

It is commonly referred to as NVENC, but it’s slightly different on Jetson in that it doesn’t use the NVENC library to access it. It is dedicated silicon within the SoC that does the encoding (not GPU).

To use it, you can use the gst-omx elements (although these are deprecated), the nvv4l2 elements, or the Jetson Multimedia API.

ok, thank you, and you say I should be able to find details in the Parker SoC TRM?

The module datasheets each have the speeds and feeds that the encoder/decoder is capable of for each module: