Initial DSIB error


case BOARD_E1627:
panel = &dsi_p_wuxga_10_1;
dsi_instance = DSI_INSTANCE_1;

[ 1.273531] isp isp.1: initialized
[ 1.275088] vic03 vic03.0: initialized
[ 1.275787] tegradc tegradc.0: DSI: HS clock rate is 464500
[ 1.277214] p,wuxga-10-1 panel dt support not available
[ 2.146386] Host read timeout at address 54400054
[ 2.649508] Host read timeout at address 5440004c
[ 3.152032] Host read timeout at address 54400054
[ 3.152153] tegradc tegradc.0: dsi: video fifo overflow. Resetting flag
[ 3.152168] tegradc tegradc.0: dsi: video fifo underflow. Resetting flag
[ 3.654661] Host read timeout at address 5440003c
[ 4.157521] Host read timeout at address 5440012c
[ 4.660109] Host read timeout at address 54400144
[ 4.662559] tegradc tegradc.0: DSI calibration timed out
[ 5.172116] Host read timeout at address 54400040
[ 5.674664] Host read timeout at address 5440003c
[ 5.674793] tegradc tegradc.0: probed
[ 5.675198] tegradc tegradc.0: fb registered

Hi yanghappyfrog,

Welcome to Jetson & Embedded Systems developer forum.
Please create the topic and issue in English manner.
Other developers can understand your issue and to share their experience with you quickly if they ever met similar issue in design stage.
And then other users could be leverage from this issue to get benefits.

Thank you.

You may lost include the panel device tree in your device tree like below.

#include "panel-p-wuxga-10-1.dtsi"

Hi ShaneCCC,
Thanks for you help.
Add this file, The problem remains unsolved.
I work on jtk1-android-l-open-source.

Hi happy
Try to use the dtc tools to reverse your dtb file to check this panel declaration really include to your dtb file.

Hi ShaneCCC,
In dsi.c file,init DSIB,why read DSI_INSTACE_0?

unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
unsigned long ret;
ret = readl(dsi->base[DSI_INSTANCE_0] + reg * 4);
trace_display_readl(dsi->dc, ret, dsi->base[DSI_INSTANCE_0] + reg * 4);
return ret;

Hi yanghappyfrog

I work on jtk1-android-l-open-source.
Just realize that your issue is on Android, maybe there will be a bit different.
Have you clarified and resolved that problem?


Hi kayccc,
No.Do you have any good idea?

tegra_dsi_readl() can read from any of the two DSI controllers’ registers, both are supposed to be identical for ganged mode. Hence we read from INSTANCE_0.

APIs tegra_dsi_controller_writel() and tegra_dsi_controller_readl() were introduced to take care of writing/reading individual DSI controller’s registers.