Good afternoon. As I’ve done with other Jetson devices, I’m trying to understand the power rail layout of the Orin. I haven’t been able to conclusively determine this from the existing documentation like the L4T docs or the Product Design Guide. Per the former, there are four active INA3221 channels: 3 on 0x40: VDD_GPU_SOC , VDD_CPU_CV, and VIN_SYS_5V0; 1 on 0x41: VDDQ_VDD2_1V8AO.
For example, are VDD_GPU_SOC and VDD_CPU_CV subsets of (branch downstream from) VIN_SYS_5V0? Is VDDQ_VDD2_1V8AO in parallel to VIN_SYS_5V0, or is it also also a child of VIN_SYS_5V0?