Good afternoon. As I’ve done with other Jetson devices, I’m trying to understand the power rail layout of the Orin. I haven’t been able to conclusively determine this from the existing documentation like the L4T docs or the Product Design Guide. Per the former, there are four active INA3221 channels: 3 on 0x40:
VIN_SYS_5V0; 1 on 0x41:
For example, are
VDD_CPU_CV subsets of (branch downstream from)
VDDQ_VDD2_1V8AO in parallel to
VIN_SYS_5V0, or is it also also a child of
Hi, VDD_GPU_SOC and VDD_CPU_CV are included to SYS_VIN_HV, VIN_SYS_5V0 is for SYS_VIN_MV, and VDDQ is included to VIN_SYS_5V0.
Thanks for the information! So if I understand correctly, the tree structure for the power sources and monitors is like:
|-- VDD_GPU_SOC (0x40, channel 1)
|-- VDD_CPU_CV (0x40, channel 2)
|-- VIN_SYS_5V0 (0x40, channel 3)
|-- VDDQ_VDD2_1V8AO (0x41, channel 2)
VDDQ_VDD2_1V8AO is the only power monitor channel that is a subset of another (
Yes, and VIN_SYS_5V0 is SYS_VIN_MV.
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