Meaning of power rail channels

Autonomous Machines Jetson & Embedded Systems Jetson Xavier NX
1

I found the following table at this link for Xavier NX.

Rail Name Description
Channel 0: 5V_IN System 5V power rail
Channel 1: VDD_CPU_GPU CPU + GPU combined power rail
Channel 2: VDD_SOC SoC power rail

What is the difference between System 5V power rail and SoC power rail? Does one of them include the power consumed by the developer board as well?

Also, I found the following table for Jetson Nano.

Rail Name Description
Channel 0: VDD_IN Main module power input.
Channel 1: VDD_GPU GPU power rail.
Channel 2: VDD_CPU CPU power rail.

Does “Main module power input” mean everything except developer board?

3

Yes, system 5V is for module only, CPU and GPU rails are from it.

4

Thanks.

BTW, I found that there are no power values at /sys/bus/i2c/drivers/ina3221x/7-0040/iio:device0 as mentioned in the documentation. Is there any change in the path with Jetpack 5.0.2 on Xavier NX?

However, I could find everything I needed at /sys/bus/i2c/drivers/ina3221x/6-0040/iio:device0/ on Jetson Nano running Jetpack 4.6.1 as mentioned in the documentation.

6

please check /sys/bus/i2c/devices/7-0040/hwmon/hwmon5.

7

Thanks!
I had to use /sys/bus/i2c/devices/7-0040/hwmon/hwmon4 though.

Any reason why the location mentioned in the documentation doesn’t work?

Also, what are channels 4-7 belong to? I see the following when I do ‘ls’ in that directory.

image
image853×226 75.3 KB

9

@WayneWWW @Trumany
Any update on what channels 4-7 belong to?

10

hello pramodhrachuri,

please check $ cat in*_label for the details.
furthermore,
in4_input shows the voltage of INA3221_CHANNEL1,
in5_input shows the voltage of INA3221_CHANNEL2,
in6_input shows the voltage of INA3221_CHANNEL3,

11

Hi Jerry,
Thanks for the response. $ cat in*_label has provided me with the following values.

==> in1_label <==
VDD_IN

==> in2_label <==
VDD_CPU_GPU_CV

==> in3_label <==
VDD_SOC

==> in7_label <==
sum of shunt voltages

No labels for in4_input, in5_input, in6_input though. Where are the INA3221_CHANNEL[1,2,3] connected? Are they same as VDD_IN, VDD_CPU_GPU_CV and VDD_SOC?

12

didn’t I just explain what they’re in previous comment #10.

14

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