Jetson AGX Orin not booting on custom carrier board

Good morning,

I am trying to boot the Orin on our custom board, which has an EEPROM that is currently empty. To bypass reading the EEPROM on the carrier board, I modified the file Linux_for_Tegra/bootloader/tegra234-mb2-bct-common.dtsi (the MB2 BCT file), changing cvb_eeprom_read_size = <0x100> to cvb_eeprom_read_size = <0x0>. I then compiled the code and flashed it, but the result remained the same.

On our custom board, only UART2 is connected. I would like to redirect the UART3 debug output to UART2 so I can view the log and identify why the boot process is not starting.

How can I do this?

Our custom board is a replica of the NVIDIA carrier board dev kit but includes only the following ports: one USB, one Ethernet, one HDMI, and one SD card.

Could the absence of other connected devices cause a problem for the Orin?
Do I need to modify the device tree?

Thank you

1 Like

I don’t think this is the solution to the Orin boot issue.
I will wait for other responses.

Thanks

@KevinFFF

I believe you will have to modify the CMDLINE_ADD variable in your flash config, specifically this portion (copied from p3701.conf): console=ttyTCU0,115200 console=ttyAMA0,115200.

When we were bringing up a custom board on AGX Orin, we ran into an issue where the developer kit flash config specified an MGBE configuration for UPHY2 in ODMDATA, but our board did not support MGBE causing the boot to fail:

From Jetson AGX Orin Platform Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide 1 documentation

You must change gbe-uphy-config from 22 to 0 or 1 if your CVB is not using MGBE. The board will not boot without this required change.

Hi giulio.bonciani1,

What’s the Jetpack version in use?

Do you mean the debug UART not present on your custom carrier board?

You can refer to Custom carrier board debugging/not booting - #14 by KevinFFF for how we redirect the log to other UART interface which has been verified with JP5.

What’s the UART2 you mean?
Do you mean uarte@3140000?
You can also refer to Jetson/L4T/peripheral/ - eLinux.org for the UART mapping.

Do you mean the debug UART not present on your custom carrier board?

yes, the debug UART isn’t present.

What’s the UART2 you mean?

yes, the SOM module UART2 that in our carrier it’s directly connected to a header without any debug MCU in the middle.

For what concern the

Custom carrier board debugging/not booting - #14 by KevinFFF

i need some help, i will follow this steps, correct me if some step is wrong, and answer to my doubts:

Step 1) i need to change the Linux_for_Tegra/p3701.conf.common in this part of code instead of ttyS1 should i write ttyS4 or ttyHS4 as shown in Jetson/L4T/peripheral/ - eLinux.org?

+CMDLINE_ADD=“mminit_loglevel=4 console=ttyS1,115200 console=ttyTCU0,115200 console=ttyAMA0,115200 console=tty0 firmware_class.path=/etc/firmware fbcon=map:0 net.ifnames=0”

Step 2)

Step 2: Dissemble the “tegra234-p3701-0000-p3737-0000.dtb” dtb to dts
dtc -I dtb -O dts -o temp.dts tegra234-p3701-0000-p3737-0000.dtb
Step 3: Modify the content in temp.dts

for my specific case i should replace 3110000 to 3140000? or something else should be changed?

  serial@3110000 {
-compatible = "nvidia,tegra194-hsuart";
+compatible = "nvidia,tegra20-uart";
            iommus = <0x2 0x4>;
            dma-coherent;
            reg = <0x0 0x3110000 0x0 0x10000>;
            reg-shift = <0x2>;
            interrupts = <0x0 0x71 0x4>;
            nvidia,memory-clients = <0xe>;
            dmas = <0x3 0x9 0x3 0x9>;
            dma-names = "rx", "tx";
            clocks = <0x4 0x9c 0x4 0x66>;
            clock-names = "serial", "parent";
            resets = <0x4 0x65>;
            reset-names = "serial";
            status = "okay";
            phandle = <0x320>;
    };

then if i’m not wrong also tegra234-bpmp-3701-0000-3737-0000.dtb should be disassembled the same as “tegra234-p3701-0000-p3737-0000.dtb” and change the Device tree for bpmp as follow replacing uartb with uarte for my specific case. The values remains the same or should i change somithing else?

		init {
			nafll_bpmp = <0xc5 0x0 0xc350000 0x0>;
			nafll_seu1 = <0x14f 0x0 0x1c3a9000 0x0>;
			bpmp_cpu_nic = <0x133 0xc5 0x0 0x0>;
			fr_seu1 = <0x14b 0x14f 0x0 0x0>;
			i2c_slow = <0x8a 0x121 0xffffffff 0x0>;
			aon_i2c_slow = <0x75 0x121 0xffffffff 0x0>;
			tach0 = <0x98 0xe 0x30d400 0x0>;
			tach1 = <0x16d 0xe 0x30d400 0x0>;
			i2c1 = <0x30 0x0 0x0 0x2>;
			qspi0_2x_pm = <0xc0 0x0 0x0 0x2>;
			sdmmc4 = <0x7b 0x0 0x0 0x2>;
			seu1 = <0x150 0x0 0x0 0x8>;
			uartc = <0x9d 0x0 0x0 0x8>;
			uarta = <0x9b 0x66 0x1c1b40 0x8>;
+			uartb = <0x9c 0x66 0x1c1b40 0x8>;
			pllref_vcoout = <0x120 0x0 0x0 0xa>;
			eqos_tx_divider = <0x19f 0x0 0xffffffff 0x0>;
			eqos_axi = <0x20 0x0 0x7735940 0x2>;
			eqos_tx = <0x23 0x0 0x0 0x2>;
			eqos_macsec_tx = <0x19e 0x0 0x0 0x2>;
			eqos_ptp_ref = <0x21 0x0 0xffffffff 0x2>;
		};

Step 3)

Assemble the dts back to dtb for both the files, right?

dtc -I dts -O dtb -o tegra234-p3701-0000-p3737-0000.dtb temp.dts
dtc -I dts -O dtb -o tegra234-bpmp-3701-0000-3737-0000.dtb temp2.dts

Step 4)
i have now all the file modified in the Linux_for_tegra folder. then i must run

sudo ./apply_binaries.sh

and then i can flash with

sudo ./flash.sh jetson-agx-orin-devkit mmcblk0p1

is this procedure enough?

EXTRA POINT) Finally, I’ve one doubt. I saw in another thread (How to enable UART?) that in the file “tegra234-cvm-p3701.dtsi” the uart should be “okay” and not “disabled”. As default in JetPack 5.1.3 the serial@3140000 seems disabled. The previous steps automatically change this field, or should i change also this file before the Step 4?

Then i think we should do also what @D3_jshaffer said, but for the moment i would be happy to see serial log.
I thank you both for the help, and i wait for some confirms.
Best Regards

Do you confirm that you are using the following UART2?

UART2 => UART5(PY05, PY06, PY07, PZ00): uarte@3140000 (serial4) - /dev/ttyTHS4

or you are using the following one?

UART5 => UART2(PX04, PX05, PX06, PX07): uartb@3110000 (serial1) - /dev/ttyTHS1

It depends on the aliases and the serial driver you used. They can be determined by device tree.
Please share the full device tree and dmesg for further check.

For UART2, you should configure serial@3140000 node.

Yes, serial@3140000 is uarte so that you should configure uarte as the following value.

+ uarte = <0x9f 0x66 0x1c1b40 0x8>;

should be.

There may be several dts in source. tegra234-cvm-p3701.dtsi seems a root dts and some nodes inside may be over-written by other dts included.
Please just check the final DTB in use to confirm if the required node is enabled.

Thank you, @KevinFFF and @D3_jshaffer, for your prompt responses.
Yes, I am using:

UART2 => UART5 (PY05, PY06, PY07, PZ00): uarte@3140000 (serial4) - /dev/ttyTHS4

Following your advice, I managed to enable UART2.
Thank you!

Additionally, our carrier board does not support MGBE, so as recommended by @D3_jshaffer, I modified the ODMDATA line in the p3701.conf.common file to:

ODMDATA=“gbe-uphy-config-0,hsstp-lane-map-3,hsio-uphy-config-16,nvhs-uphy-config-0”;

This disabled MGBE. With these changes, the Orin finally booted and provided all the information through the serial console.

NEW PROBLEM: Now the remaining problem is that the RGMII Ethernet is not enabled and therefore does not work.
After reading the guide “Jetson AGX Orin Platform Adaptation and Bring-Up”, suggested by @D3_jshaffer, in the chapter “Ethernet Controller Configuration” - “For RGMII”, we understand that we need to modify the pinmux.

To do that, I think we need to enable the RGMII pins on the pinmux spreadsheet provided and generate the dts files, or alternatively manually modify the dts with code reported in the link, correct?

Howewer we don’t understand in what file we have to insert this code reported

phy-mode = "rgmii-id";
phy-handle = <$phy>;
nvidia,phy-reset-gpio = <$tegra_main_gpio TEGRA234_MAIN_GPIO(g, $) 0>mdio {
    compatible = "nvidia,eqos-mdio";
    #address-cells = <1>;
    #size-cells = <0>;
    phy: phy@1 {
        reg = <1>;
        nvidia,phy-rst-pdelay-msec = <224>; /* msec */
        nvidia,phy-rst-duration-usec = <10000>; /* usec */
        interrupt-parent = <$tegra_main_gpio>;
        interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
   };
};

After this modifications the ethernet should start?

Additionally, I would like to inform you that we are using the KSZ9031RNX as the Ethernet chip.

QUESTION: How can I enable it? Could you better explain the steps and modifications required?

Thank you all!

It seems you can enable UART2 for debug messages and the board can boot up successfully.

For new RGMII Ethernet issue, please open another topic to discuss in details.
Or you can refer to UEFI RGMII - #12 by velorin0 for the configuration in device tree.

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