Jetson AGX Orin - SPI interface with 2-CH CAN FD HAT(MCP2518FD) SPI Module

dingbobby · August 4, 2024, 3:43pm

Hi,

I am now using the Jetpack36.3. My Jetson AGX Orin 32GB is 3737.

Because the number of the interface CAN is not enough in our senario, we want extend more CAN interface with MCP2518FD.

With this link Jetson Orin - SPI interface with MCP2518 SPI Module I tested the loopback of spi.

I modified the code of GitHub - Seeed-Studio/seeed-linux-dtoverlays: Device Tree Overlays for Seeed boards to adapt the kernal of 36.3 and the compilation is successful.

At the step of the modification of the device tree, I found that the kernal source of 36.3 is different with 35.5 which I found exactly the file “sources/hardware/nvidia/platform/t23x/concord/kernel-dts/cvb/tegra234-p3737-0000-a04.dtsi”. Could you please help me with this?

Which are the files that I need to modify and what are the modifications in these files?

Thanks a lot in advance.

Best regards,

Feng DING

KevinFFF · August 6, 2024, 9:38am

Hi dingbobby,

Are you using the devkit or custom board for AGX Orin?

Please refer to MCP2515 Verification for the verification of MCP2515 on both R35.4.1 and R36.3.0.
It should be the similar steps for your MCP2518FD module.

dingbobby · August 7, 2024, 9:29am

Hi KevinFFF,

Thanks a lot for your response, the link that you shared is very useful.

Are you using the devkit or custom board for AGX Orin?

Answer: I think so, the model type is P3701-0000 for orin, P3737-0000 for the carrier board.

BTW, I checked the dtb file on my target device which showed that the FDT is FDT /boot/dtb/kernel_tegra234-p3737-0000+p3701-0000-nv.dtb. As I understood, P37xx means the different product model of Jetson Orin. the example in the Jetson/L4T/peripheral/ - eLinux.org modified the file tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi which used to build tegra234-p3768-0000+p3767-0000-nv.dtb.

The descriptions above means we used the different model of Jetson AGX orin?
As what I understood, I need to modify the tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi file at my side and use the file tegra234-p3701-0000+p3737-0000-nv.dtb to replace on the target? Is it correct?

tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi and tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi has a lot of differences. And I did not find the code below at part bus@0. I just copy the code below from tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi to tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi?

/* SPI1, 40pin header, Pin 19(MOSI), Pin 21(MISO), Pin 23(CLK), Pin 24(CS) */
		spi@3210000{
			status = "okay";
			spi@0 {
				compatible = "microchip,mcp2518fd";
				reg = <0x0>;
				spi-max-frequency = <2000000>;
				interrupt-parent = <&gpio>;
				interrupts = <TEGRA234_MAIN_GPIO(Q, 5) IRQ_TYPE_LEVEL_LOW>;
				clocks = <&can_clock>;
				nvidia,enable-hw-based-cs;
				controller-data {
					nvidia,enable-hw-based-cs;
					nvidia,rx-clk-tap-delay = <0x10>;
					nvidia,tx-clk-tap-delay = <0x0>;
				};
			};
			spi@1 {
				compatible = "tegra-spidev";
				reg = <0x1>;
				spi-max-frequency = <50000000>;
				controller-data {
					nvidia,enable-hw-based-cs;
					nvidia,rx-clk-tap-delay = <0x10>;
					nvidia,tx-clk-tap-delay = <0x0>;
				};
			};

		};

		/* SPI3, 40pin header, Pin 37(MOSI), Pin 22(MISO), Pin 13(CLK), Pin 18(CS) */
		spi@3230000{
			status = "okay";
			spi@0 {
				compatible = "tegra-spidev";
				reg = <0x0>;
				spi-max-frequency = <50000000>;
				controller-data {
					nvidia,enable-hw-based-cs;
					nvidia,rx-clk-tap-delay = <0x10>;
					nvidia,tx-clk-tap-delay = <0x0>;
				};
			};
			spi@1 {
				compatible = "tegra-spidev";
				reg = <0x1>;
				spi-max-frequency = <50000000>;
				controller-data {
					nvidia,enable-hw-based-cs;
					nvidia,rx-clk-tap-delay = <0x10>;
					nvidia,tx-clk-tap-delay = <0x0>;
				};
			};
		};

Sorry for the standard question.

Best regrads,

Feng

KevinFFF · August 11, 2024, 1:37pm

Correct! You should modify tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi for AGX Orin.
However, the verification we did is based on Orin NX.

Please share your this dtsi file for further check.

dingbobby · August 18, 2024, 3:40pm

Thanks for your confirm.
This is the content of the file that I tried to compile.

// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.

#include "nv-soc/tegra234-overlay.dtsi"
#include "nv-soc/tegra234-soc-thermal.dtsi"
#include "nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi"
#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
#include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
#include "nv-soc/tegra234-soc-camera.dtsi"
#include "tegra234-p3737-0000.dtsi"
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"

/ {
	cpus {
		idle-states {
			c7 {
				status = "okay";
			};
		};
	};

	nvpmodel {
		status = "okay";
	};

	scf-pmu {
		status = "okay";
	};

	soctherm-oc-event {
		status = "okay";
	};

	thermal-zones {
		cpu-thermal {
			status = "okay";
		};

		cv0-thermal {
			status = "okay";
		};

		cv1-thermal {
			status = "okay";
		};

		cv2-thermal {
			status = "okay";
		};

		gpu-thermal {
			status = "okay";
		};

		soc0-thermal {
			status = "okay";
		};

		soc1-thermal {
			status = "okay";
		};

		soc2-thermal {
			status = "okay";
		};
	};

	bus@0 {
		smmu_test {
			compatible = "nvidia,smmu_test";
			iommus = <&smmu_niso0 TEGRA234_SID_SMMU_TEST>;
			status = "okay";
		};

		pinmux@2430000 {
			status = "okay";
		};

		ufshci@2500000 {
			status = "okay";
		};

		aconnect@2900000 {
			ahub@2900800 {
				i2s@2901200 {
					status = "okay";
				};

				i2s@2901400 {
					status = "okay";
				};

				dmic@2904000 {
					status = "okay";
				};

				dmic@2904100 {
					status = "okay";
				};

				dmic@2904300 {
					status = "okay";
				};

				dspk@2905000 {
					status = "okay";
				};

				dspk@2905100 {
					status = "okay";
				};

				afc@2907000 {
					status = "okay";
				};

				afc@2907100 {
					status = "okay";
				};

				afc@2907200 {
					status = "okay";
				};

				afc@2907300 {
					status = "okay";
				};

				afc@2907400 {
					status = "okay";
				};

				afc@2907500 {
					status = "okay";
				};

				arad@290e400 {
					status = "okay";
				};
			};
		};

		serial@3110000 {
			compatible = "nvidia,tegra194-hsuart";
			reset-names = "serial";
			status = "okay";
		};

		i2c@3180000 {
			status = "okay";
		};

		i2c@3190000 {
			status = "okay";
		};

		i2c@31b0000 {
			nvidia,hw-instance-id = <0x5>;
			status = "okay";
		};

		i2c@31c0000 {
			status = "okay";
		};

		serial@31d0000 {
			current-speed = <115200>;
		};

		i2c@31e0000 {
			status = "okay";
		};

		tachometer@39c0000 {
			status = "okay";
		};

		hsp@3d00000 {
			status = "okay";
		};

		ethernet@6800000 {
			status = "okay";
		};

		aon@c000000 {
			status = "okay";
		};

		hardware-timestamp@c1e0000 {
			status = "okay";
			nvidia,num-slices = <3>;
		};

		i2c@c240000 {
			status = "okay";
		};

		hdr40_i2c1: i2c@c250000 {
			status = "okay";
		};

		can_clock: can_clock {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
			clock-accuracy = <100>;
		};

		/* SPI1, 40pin header, Pin 19(MOSI), Pin 21(MISO), Pin 23(CLK), Pin 24(CS) */
		spi@3210000{
			status = "okay";
			spi@0 {
				compatible = "microchip,mcp2518fd";
				reg = <0x0>;
				spi-max-frequency = <2000000>;
				interrupt-parent = <&gpio>;
				interrupts = <TEGRA234_MAIN_GPIO(Q, 5) IRQ_TYPE_LEVEL_LOW>;
				clocks = <&can_clock>;
				nvidia,enable-hw-based-cs;
				controller-data {
					nvidia,enable-hw-based-cs;
					nvidia,rx-clk-tap-delay = <0x10>;
					nvidia,tx-clk-tap-delay = <0x0>;
				};
			};
			spi@1 {
				compatible = "tegra-spidev";
				reg = <0x1>;
				spi-max-frequency = <50000000>;
				controller-data {
					nvidia,enable-hw-based-cs;
					nvidia,rx-clk-tap-delay = <0x10>;
					nvidia,tx-clk-tap-delay = <0x0>;
				};
			};

		};

		rtc@c2a0000 {
			status = "okay";
		};

		mttcan@c310000 {
			status = "okay";
		};

		mttcan@c320000 {
			status = "okay";
		};

		actmon@d230000 {
			status = "okay";
		};

		hwpm@f100000 {
			status = "okay";
		};

		mc-hwpm@2c10000 {
			status = "okay";
		};

		host1x@13e00000 {
			nvjpg@15380000 {
				status = "okay";
			};

			nvdec@15480000 {
				status = "okay";
			};

			nvenc@154c0000 {
				status = "okay";
			};

			tsec@15500000 {
				status = "okay";
			};

			nvjpg@15540000 {
				status = "okay";
			};

			se@15810000 {
				status = "okay";
			};

			se@15820000 {
				status = "okay";
			};

			se@15840000 {
				status = "okay";
			};

			nvdla0@15880000 {
				status = "okay";
			};

			nvdla1@158c0000 {
				status = "okay";
			};

			ofa@15a50000 {
				status = "okay";
			};

			pva0@16000000 {
				status = "okay";

				pva0_niso1_ctx0 {
					status = "okay";
				};

				pva0_niso1_ctx1 {
					status = "okay";
				};

				pva0_niso1_ctx2 {
					status = "okay";
				};

				pva0_niso1_ctx3 {
					status = "okay";
				};

				pva0_niso1_ctx4 {
					status = "okay";
				};

				pva0_niso1_ctx5 {
					status = "okay";
				};

				pva0_niso1_ctx6 {
					status = "okay";
				};

				pva0_niso1_ctx7 {
					status = "okay";
				};
			};
		};

		gpu@17000000 {
			status = "okay";
		};
	};

	tegra-hsp@b950000 {
		status = "okay";
	};

	dce@d800000 {
		status = "okay";
	};

	tegra_mce@e100000 {
		status = "okay";
	};

	display@13800000 {
		status = "okay";
	};
};

For build the driver I used this project GitHub - Seeed-Studio/seeed-linux-dtoverlays: Device Tree Overlays for Seeed boards. And I will tried to update my modification with the driver to adapt the linux version of 36.x.

Regards,

Feng

system · September 10, 2024, 8:32am

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.