What are the logic levels (Vout low max/Vout high min) and the drive capacity (in mA) of the Jetson AGX Xavier PERST# signal on the PCIe J6 connector? Is it actively driven (push-pull output) or the open drain type? Module schematics on page 9 shows this signal as a combinations of two signals: PEX_L5_RST_N and GPIO19_SLVS_VSYNC. It may be a wired OR connection or perhaps the second GPIO19 signal is simply used to monitor the PERST# status. There is a 47K pull-up resistor to 3.3V (R839), but it is shown as not stuffed. The PERST# signal seems to be rising rather slow upon de-asserting making us think that there may be not enough current drive capacity on this signal out of the module. Should a pull-up resistor resistor be added on the plug-in PCIe card? Our FPGA card works fine in PC environment but on Xavier it is occasionally not being recognized on the PCIe bus; we think it might be related to PERST# signal peculiar behavior.
Hi, the module schematic is not public, where do you get it? The module is validated before ship-out. PCIe function has no problem during validation. If you have some concern on specific device attached, you can try changes on the device side.
I downloaded schematic from your web site. I understand that module is being validated etc, but was hoping to get a more meaningful answer.
Which web site? The module schematic is not public, what you have might be wrong including R839. As said, you can try tuning on device side as in general the root cause is not in the module since it is validated.
The schematic I have called P2822-B03 Jetson Xavier Developer Kit Carrier Board.
P2822 is carrier board, not module. There is a 4.7k pull-up inside module on PEX_L5_RST_L.
Oh, sorry, I used the wrong word!
So the module output is in fact an open drain type with 4.7K pull-up resistor – otherwise no pull-up resistor will be needed, correct?
I also saw that 4.7K pull-up resistor is recommended by NVDIA for OEM developed boards on all PCIe bus sideband signals.
Yes, it’s OD type.
Thank you very much!