I’m a confused about the PCIe link on the Jetson Nano SoM connector.
In the schematic for the Antmicro baseboard, there is more than 4 PCIe lanes.
There is PEX_0 lane up to PEX_4 and a PEX_6. There is two clock lines PEX_CLOCK_1 and PEX_CLOCK_2.
In the Antmicro schematic, PËX_6 lane is used for USB 3.0.
Can any body comment and explain all those lanes?
What about connecting the SoM to a PCIe device with 4 lanes. What lanes do I have to use?
Thanks for helping
Is this information and the schematics for the module and the carrier board available?
I’m basing my investigation on the Antmicro schematic and trying to bridge the link between your info and their design.
In their design the module pins 167,169,172,174 are not used but labled PEX_#0 so I guess it’s the Ethernet module.
My best guess is that pins 157,155,162,160 are for PCIe0, 149,151,148,150 for PCIe1, 131,133,134,136 for lane2 and 139,137,140,142 for lane 3. Am I correct?
I have a screen shots I just added.
You need to ask vendor for how their board design in detail. Jetson nano only support above one configuration.
Do Nvidia planning to release the schematic and more informations about the HW of the nano module and carrier board?
If yes when can we expect that?
Yes, we plan to release the design docs and reference carrier design files closer to the release of the production Nano module in June.