Hi everyone,
I’m working with a Jetson TK1 where it’s configured as a PCIe Root Complex, connected to two endpoints:
- An FPGA on a x1 lane
- A PowerPC processor on a x4 lane
During boot-up, the Jetson consistently establishes a link with the x1 device (FPGA). However, it intermittently fails to establish a connection with the x4 lane endpoint (PowerPC).
After investigating in kernel space (L4T R21.5, kernel 3.10.40), I noticed that the Data Link Up flag (RP_VEND_XP_DL_UP) is not set for the x4 lane, so the device is never enumerated.
I’m looking to debug this issue further and would really appreciate any suggestions or insights from the community
also at which stage of the Jetson TK1 boot process does PCIe link training occur? i want to dive into that area of debugging aswell