Please let me know the signals for GbE signals (Ethernet signals) of Jetson TX2 NX in IBIS Model for Ethernet (MDI) System level validation.
Please refer to the package in DLC: https://developer.nvidia.com/jetson-tx2-nx-series-s-parameter-ibis-files
Hi Trumany,
Thank you for the reply. I got the connection details from NVIDIA Jetson TX2 Series Pin and Function Names Guide. But the pin mapping for MDI pins to the Tegra X2 is not available. Please advice.
(I did find a S-Parameter for the MDI signals though. But I can’t find the corresponding pins on the Tegra X2)
Are you talking about TX2 or TX2 NX? If latter, please refer to the Ethernet chapter in DG: Jetson TX2 NX integrates a Realtek RTL8211F(I) Gigabit Ethernet PHY. The magnetics and RJ45 connector would be implemented on the carrier board.
Hi Trumany,
I was checking with both TX2 and TX2 NX for feasibility of a POC design planned. We need the ETH simulated results for the same. I can’t find the connection between the SoC and the PHY
and the corresponding IBIS for the RGMII and MDI signals. Please share any documents available on this.
Did you see the file “GBE_MDI_TD_SODIMM_0000001.s16p” in package? That’s for MDI. As you can see it is PHY to port.
Hi Trumany,
The file only consists of the S-parameter after the PHY. I was wondering about the IBIS (source of the signal) for both directions i.e., towards SoC and towards Connector from PHY
That’s what we can provide. Why do you want that of SoC to PHY? For your design, the port IO is what you should concern.
Thank you for the reply. Since I didn’t see any report on the SoC to PHY interface, I was hoping to simulate it too.
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