I am working on Xavier NX with L4T 35.2.1.
The voltage for the 40-pin GPIO Header pins is expected to be 3.3V. But We are seeing the voltage to be around 0.4V of the GPIO “I2S0_DOUT - PT.06” pin when made high from the sysfs entry.
When set to 0 we are seeing 0V as expected. But when it is made HIGH it is reaching only 0.4V.
We have not seen this issue in the old L4T 32.5 version but exists with 35.2.1.
Are you using the devkit or custom board for Xavier NX?
Have you tried latest R35.3.1?
Could you help to provide the command you use to pull PT.06 to high and we can reproduce locally on the devkit?
I am using Jetson Xavier NX devkit.
This was working properly with 32.5. I have not tried with 35.3.1, we just ported from 32.5 to 35.2.1. and are testing. Apart from this everything seems fine. I have tried probing with the multimeter as well as oscilloscope, but results are same.
Commands used to configure PT.06:
echo 463 > /sys/class/gpio/export
echo out > /sys/class/gpio/PT.06/direction
echo 1 > /sys/class/gpio/PT.06/value
I can confirm that, this is not an HW issue since the old version works well with this setup and have tried with 2 devkits.
Could you help to capture the pinmux condiguration of PT.06?
$cat /sys/kernel/debug/pinctrl/2430000.pinmux/pinconf-groups|grep -i pt6
Hi @KevinFFF ,
Sorry, found out to be an issue with the HW.
The voltage levels are fine with one more Jetson devkit. We have a FPGA board from lattice which isconnected to Jetson Xavier NX over 40-pin header. My motive is to flash the FPGA board from Lattice Radiant Tool. We have 3 GPIO’s from the 40 pin header which are used for this purpose.
- GPIO07 PR.00 (443) - ProgramN GPIO-> For Programming the FPGA
- I2S0_DOUT PT.06 (463) - Mux Selection GPIO → Should be 1 for flashing the FPGA board from Lattice radiant tool and should be 0 to upgrade firmware from Jetson.
- UART1_CTS PR.05 (448) - Jtag Disable → For disabling Jtag if FW upgrade to be done from Jetson.
The requirements to flash the FPGA board through the tool is to make these 3 GPIO’s HIGH.
Even though the GPIO’s are high, flashing is still failing. It fails to scan the board from the Radiant tool.
With the same HW setup and with L4T 32.5 BSP running on it, the FPGA flashing operation is successful. But fails with L4T 35.2.1.
What could be causing a failure? Apart from the L4T version there isn’t any change in FPGA board or the firmware.
So, could you pull these 3 GPIO to high with L4T 35.2.1 before flashing FPGA?
Sorry, we don’t have this FPGA board and the flashing process for this FPGA board.
Do you have any log or know which part failed during flash?
Hi @KevinFFF ,
Yes we will pull these GPIOs high before flashing the FPGA board. All the voltage levels seems to be fine 0V when pulled low and 3.3V when pulled high.
Attaching failure log and working log(with 32.5).
fpga_flash_failure_35.2.1_log.txt (3.7 KB)
fpga_success_32.5_log.txt (8.6 KB)
If the GPIO behavior is expected, I might could not help you more with FPGA update issue as I mentioned before. We don’t know your FPGA flash process, and it seems another topic to discuss with…
Okay we will debug this.
Thanks for your support : )
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