We want to use 4 lane MIPI CSI input for our custom carrier board for Nano module. As suggested in Nano product design guide, we use CSI0 and CSI1 pairs as 4 lane MIPI data and CSI0 clock as a MIPI clock.
CSI0 D0 and D1 as D0 and D1(4 lane) pairs respectively
CSI0 Clk as MIPI Clk
CSI1 D0 and D1 as D2 and D3(4 lane) pairs respectively
Please refer the attached image for reference.
Kindly confirm whether the above configuration is correct.