1. HW connections:
TX1 supports eight total MIPI DSI data lanes and two clock lanes, allowing up to two 4-lane interfaces.
TX1 supports three MIPI CSI x4 bricks, allowing a variety of device types and combinations to be supported. Up to two quad lane stereo cameras or 6 dual camera streams are available.
2. Routing guide:
3. Links of reference docs:
JetsonTX1_OEM_Product_DesignGuide.pdf, chapter 7.0&8.0:
Tegra X1 (SoC) Data Sheet for Jetson TX1, chapter 3.4&3.11:
Tegra X1 (SoC) Technical Reference Manual, chapter 24, 26, 29, 30, 31: