I am currently working on a system where the NVIDIA Jetson Orin NX acts as the PCIe host and an FPGA implementing the AMD Xilinx QDMA IP acts as the PCIe endpoint in ZU7EV.
The objective is to achieve high-speed data transfer between the FPGA and the Jetson platform over PCIe. I would like to understand whether the Jetson Orin NX PCIe root complex is fully compatible with a QDMA-based FPGA endpoint and if there are any known limitations when integrating these two platforms. I also want to know whether the standard Xilinx QDMA Linux driver can run on the Jetson’s ARM64 Linux environment or if modifications are required to build and run it on the Jetson kernel. Additionally, I would like clarification on whether any special device tree configuration is needed on the Jetson for detecting and working with a custom PCIe endpoint such as QDMA, or if normal PCIe enumeration is sufficient. It would also be helpful to know how BAR regions exposed by QDMA are mapped in the Jetson Linux environment, whether MSI/MSI-X interrupts from the FPGA endpoint are supported correctly, and what kind of throughput can be expected when using QDMA over PCIe Gen4 between the FPGA and Jetson. Finally, I am also interested in understanding whether it is possible to integrate QDMA transfers with NVIDIA GPUDirect so that data from the FPGA can be transferred directly into GPU memory on the Jetson platform. Any guidance, documentation references, or example implementations using Jetson Orin NX with Xilinx QDMA would be greatly appreciated.
We don’t have much experience on integrating the Xilinx FPGA, but you may refer the When the TX2 NX reads data from the PCIe device, errors occur probabilistically - Jetson Systems / Jetson TX2 - NVIDIA Developer Forums, which successful integrate it with Jetson TX2, suppose should be OK with Orin NX.
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