From nvpps.txt:
NVIDIA nvpps driver bindings
Nvpps is a Linux Kernel mode driver to support the Xavier & Orin time domain
correlation feature.
Required properties:
- compatibles: should be “nvpps,tegra194-nvpps”
Optional properties:
- gpios: GPIO number and active level for the PPS input signal
- memmap_phc_regs: boolean flag to indicate MAC PHC regs to be memory mapped
for getting PTP time. If not defined ptp notifer method will
be used with selected interface - interface: NW interface name to be used for MAC PHC regs. This field can be
set to ‘eqos_0’, ‘mgbe0_0’, ‘mgbe1_0’, ‘mgbe2_0’ or ‘mgbe3_0’ for Orin.
For Xavier, it shoud be set to ‘eqos_0’. If undef, default to ‘eqos_0’ - sec_interface: NW interface name to be used to calculate PTP Time offset.
set to ‘eqos_0’, ‘mgbe0_0’, ‘mgbe1_0’, ‘mgbe2_0’ or ‘mgbe3_0’ for Orin.
For Xavier, Leave this undefined. For Orin, If undef default to ‘eqos_0’ - ptp_tsc_k_int: Specifies the integer part of the factor used to calculate the delta to
apply to NUM when the fast convergence algorithm is enabled when syncing
or locking TSC time with PTP time domain.
The value is a 8bit hexa-decimal value. If unspecified, NvPPS driver uses
0x70 as default value - ptp_tsc_lock_threshold: specifies the threshold value which is used by HW to determine
if the TSC PTP sync/Lock is lost. The lock is deemed to be lost if the HW
determined absolute diff between PTP & TSC time exceed this value.
The value is a 16bit hexa-decimal value. The minimum value(0x1F) supported
correspond to 1us and max value(0xFFFF) supported correspond to approx 2.1ms.
If unspecified, NvPPS driver uses 0x26C(corresponding to 20us) by default - ptp_tsc_sync_dis: boolean flag to indicate if nvpps should disable PTP TSC sync logic.
The default behaviour is to keep PTP TSC sync logic enabled.
(bolding mine)
The relevant dtsi entry (drive-linux/kernel/source/hardware/nvidia/platform/t23x/automotive/kernel-dts/p3710/common/tegra234-p3710-0010.dtsi)
nvpps {
compatible = "nvidia,tegra194-nvpps";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0xc6a0104 0x0 0x118>;
interface = "mgbe2_0";
sec_interface = "eqos_0";
status = "disabled";
};
Based on this, I would expect that the it would attempt to syntonize TSC to mgbe2_0’s PHC (/dev/ptp2, for the record) with a K value of 0x70 and locking threshold of 20uS.