Orin MIPI CSI-2 lane swapping with JetPack 6

[jetson-developer]

Hello,

Is it possible to do MIPI CSI-2 lane swapping on Orin AGX/NX with JetPack 6, similar to LANE_SWIZZLE_CTRL from Xaviers? I read some forum-posts and it seemed that this feature hasn’t previously been supported with Orin-devices due to missing RCE implementation. I believe at least some changes/improvements have been made to RCE firmware with the new JetPack, TRM hasn’t been updated after v1.2 so not holding my breath :)

BR, jetson-developer

[jetson-developer]

May have just gotten my answer as I diffed csi5_registers.h between JetPack 5.1.2 and 6.1 and there appears to be no changes/additions to the register definitions.

Still would appreciate any insight whether this is going to be implemented, or is it even feasible with Orins’ on-board CSI bricks + RCE?

-jetson-developer-

[JerryChang]

hello jetson-developer,

may I have confirmation,
what’s the capture pipeline you’re used, would you like to have data-lane swapped? (i.e. D0 ↔ D1).

[jetson-developer]

Hello JerryChang,

Yes, I’d like to be able to change the datalane order. I have a native V4L2 application on top of VI providing frames.

-jetson-developer-

[JerryChang]

hello jetson-developer,

we do not support the data-lane swizzle through Argus,
but, please give it a try to update brick_config.lane_swizzle, and test the capture pipeline via V4L2.
for instance,
$public_sources/kernel_src/kernel/nvidia-oot/drivers/media/platform/tegra/camera/nvcsi/csi5_fops.c

static int csi5_stream_set_config()
{
...
	/* Brick config */
	memset(&brick_config, 0, sizeof(brick_config));
	brick_config.phy_mode = (!is_cphy) ?
		NVCSI_PHY_TYPE_DPHY : NVCSI_PHY_TYPE_CPHY;
+	brick_config.lane_swizzle = NVCSI_LANE_SWIZZLE_A1A0B0B1;

[jetson-developer]

Hi JerryChang,

thanks for your response, we’ll give it a try

-jetson-developer-