PCI-E Bus Error

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX1
1

I have a carried board with TX1 module. When the DP port plugs-in, then I get the following log, Seems the PCIe Bus received some error packages, but the PCIE port seems works.

Any suggestions on this?

[  424.841272] tegradc tegradc.0: dp: plug event received
[  424.847040] hpd: state 3 (Disabled), hpd 1, pending_hpd_evt 1
[  424.853788] hpd: switching from state 3 (Disabled) to state 0 (Reset)
[  424.899665] hpd: state 0 (Reset), hpd 1, pending_hpd_evt 0
[  424.905244] hpd: hpd_switch 0
[  424.908309] hpd: switching from state 0 (Reset) to state 1 (Check Plug)
[  424.923659] hpd: state 1 (Check Plug), hpd 1, pending_hpd_evt 0
[  424.923666] hpd: switching from state 1 (Check Plug) to state 2 (Check EDID)
[  424.985575] hpd: state 2 (Check EDID), hpd 1, pending_hpd_evt 0
[  425.014792] tegradc tegradc.0: mode bw=11744870400 > link bw=8640000000
[  425.030921] tegradc tegradc.0: mode bw=9953280000 > link bw=8640000000
[  425.031898] tegradc tegradc.0: mode bw=12740198400 > link bw=8640000000
[  425.032854] tegradc tegradc.0: mode bw=10616832000 > link bw=8640000000
[  425.041500] tegradc tegradc.0: mode bw=11943936000 > link bw=8640000000
[  425.046905] tegradc tegradc.0: mode bw=12740198400 > link bw=8640000000
[  425.051380] tegradc tegradc.0: mode bw=11943936000 > link bw=8640000000
[  425.054582] hpd: Display connected, hpd_switch 1
[  425.054623] hpd: switching from state 2 (Check EDID) to state 4 (Enabled)
[  428.405164] tegradc.0 supply avdd_3v3_dp not found, using dummy regulator
[  428.405260] max77620-gpio7: supplied by vdd-gen-pll-edp
[  428.408943] pcieport 0000:00:01.0: AER: Multiple Corrected error received: id=0010
[  428.408953] pcieport 0000:00:01.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, id=0008(Receiver ID)
[  428.408957] pcieport 0000:00:01.0:   device [10de:0fae] error status/mask=00000001/00002000
[  428.408960] pcieport 0000:00:01.0:    [ 0] Receiver Error         (First)
[  428.719813] tegradc tegradc.0: nominal-pclk:297000000 parent:297000000 div:1.0 pclk:297000000 294030000~323730000
[  428.739419] tegradc tegradc.0: DP : Prod set failed
[  428.741278] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 1
[  428.741312] dp lt: switching from state 0 (Reset) to state 0 (Reset)
[  428.741374] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[  428.744253] tegradc tegradc.0: DP : Prod set failed
[  428.744653] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[  428.744758] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[  428.745778] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[  428.745816] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[  428.745847] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[  428.745877] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[  428.748261] dp lt: CR not done
[  428.749988] dp lt: new config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  428.750016] dp lt: new config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  428.750036] dp lt: new config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  428.750056] dp lt: new config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  428.750075] dp lt: CR retry
[  428.750104] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[  428.750207] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[  428.750282] dp lt: config: lane 0: vs level: 1, pe level: 0, pc2 level: 0
[  428.750314] dp lt: config: lane 1: vs level: 1, pe level: 0, pc2 level: 0
[  428.750346] dp lt: config: lane 2: vs level: 1, pe level: 0, pc2 level: 0
[  428.750377] dp lt: config: lane 3: vs level: 1, pe level: 0, pc2 level: 0
[  428.756753] dp lt: CR done
[  428.756787] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[  428.756858] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[  428.760297] dp lt: CE not done
[  428.761631] dp lt: new config: lane 0: vs level: 1, pe level: 2, pc2 level: 0
[  428.761644] dp lt: new config: lane 1: vs level: 1, pe level: 2, pc2 level: 0
[  428.761654] dp lt: new config: lane 2: vs level: 1, pe level: 2, pc2 level: 0
[  428.761663] dp lt: new config: lane 3: vs level: 1, pe level: 2, pc2 level: 0
[  428.761690] dp lt: config: lane 0: vs level: 1, pe level: 2, pc2 level: 0
[  428.761706] dp lt: config: lane 1: vs level: 1, pe level: 2, pc2 level: 0
[  428.761722] dp lt: config: lane 2: vs level: 1, pe level: 2, pc2 level: 0
[  428.761738] dp lt: config: lane 3: vs level: 1, pe level: 2, pc2 level: 0
[  428.762243] dp lt: CE retry
[  428.762255] dp lt: switching from state 3 (channel equalization) to state 3 (channel equalization)
[  428.762296] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[  428.765770] dp lt: CE done
[  428.765785] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[  428.765855] dp_audio switch 1
nvidia@tegra-ubuntu:~$
nvidia@tegra-ubuntu:~$ lspci
00:01.0 PCI bridge: NVIDIA Corporation Device 0fae (rev a1)
01:00.0 Network controller: Intel Corporation Wireless 3160 (rev 83)
nvidia@tegra-ubuntu:~$
2

Hi jjc_0115,

Could you share the schematic of your carrier board?

3

Hi WayneWWW,

Sorry for the late reply, I attached some part of schematic related to the PCIE issue.

We have another similar carried board without this issue. Since, we changed some PCIE pins(Please refer to the attachment) for the compatible with TX1/TX2 module, and the PCIE issue occurred.
And we also we disabled the pcie-m2 in the DTS.

pcie-m2 {
				nvidia,lanes = "uphy-lane-0";
				nvidia,function = "pcie";
				nvidia,pcie-controller = <1>;
				nvidia,pcie-lane-select =
					<TEGRA_PADCTL_PCIE_LANE_X1>;
				status = "disabled"; 
			};

TX1_PCIE ERROR PART.pdf (441 KB)

4

Hi,
Can you check the OEM Design guide, Jetson TX1 USB 3.0, PCIe & SATA Lane Mapping Configurations, how many SATA, USB3 and PCIe(how many data lane for each) you have? Which Configurations you want use?
And check your BSP document like https://developer.nvidia.com/embedded/dlc/l4t-documentation-28-1
Tegra_Linux_Driver_Package_TX1_Adaptation_Guide, there have example how to configurate USB/SATA/PCIe lanes.

From hardware, unused USB/PCIe/SATA RX lanes should be connect to GND.