PCIe 12V arrives too late for PERST

We found an issue with the Jetson AGX Xavier that NVIDIA may find interesting.

The problem is Xavier Jetson AGX does not start to operate with some high end SSDs (The setup is just Intel Optane SSD connected to the Xavier).
With some PCIe switches between the NVIDIA and the SSD there is no problem.

Our suspicion is the Xavier’s PCIe 12V is raised after the reset period (PCIe PERST signal) is complete.
That is, an SSD, that requires 12v, will receive the 12v after the 3.3v is up, and reset (PESRT) was complete. That is miss the reset period.

Whereas according to PCIe standard, it should raise the PERST only 100milisec after both 3.3 and 12v are power good.

The questions

  1. Is it a known issue with the NVIDA? Or this sequence is intentional? Can it be changed?
  2. If this sequence is intentional, can you help us with the reasons for it?

More details from the lab experiments. Xavier perform the following sequence on boot:
TIME0 – PCIe power 3.3V is raised
TIME1 – PCIe PERST is raised
TIME2 – 12V power is raised

TIME1-TIME0 = ~8ms
TIME2-TIME0 = ~300ms

This is not expected.
Can you tell me which release are you using?

Jetson AGX XAVIER development kit

Xavier kernel version:

Can you please try with the latest release? i.e. Jetpack 32.2?

We will try it.
Meanwhile, is there an option to control the PERST from SW?

Issue seems to be resolved with the above release.

Good to know that.
Thanks for the update.