Please provide the following info (tick the boxes after creating this topic): Software Version
DRIVE OS 6.0.8.1
[*] DRIVE OS 6.0.6
DRIVE OS 6.0.5
DRIVE OS 6.0.4 (rev. 1)
DRIVE OS 6.0.4 SDK
other
Target Operating System
[*] Linux
QNX
other
Hardware Platform
DRIVE AGX Orin Developer Kit (940-63710-0010-300)
[*] DRIVE AGX Orin Developer Kit (940-63710-0010-200)
DRIVE AGX Orin Developer Kit (940-63710-0010-100)
DRIVE AGX Orin Developer Kit (940-63710-0010-D00)
DRIVE AGX Orin Developer Kit (940-63710-0010-C00)
DRIVE AGX Orin Developer Kit (not sure its number)
other
SDK Manager Version
1.9.3.10904
[*] other
Host Machine Version
[*] native Ubuntu Linux 20.04 Host installed with SDK Manager
native Ubuntu Linux 20.04 Host installed with DRIVE OS Docker Containers
native Ubuntu Linux 18.04 Host installed with DRIVE OS Docker Containers
other
I find the default UPHY1 and pcie config as below:
3、So, is the default 4 lane config for UPHY1 to pcie correct ? In this develop kit (DRIVE AGX Orin Developer Kit (940-63710-0010-200)) and SDK (DRIVE OS 6.0.6 & Linux) can config UHPY1 to 2 pcie 4 lane,if yes or not, how to modify?
Dear @huangxx8,
May I know when you notice this issue like flashing or compilation?. Did you make any changes or noticed issue with default files in DRIVE OS?
1、We want to use “nvscistream_event_sample” to test nvscic2c_pcie function, I follow " Chip to Chip Communication | NVIDIA Docs " when excute “sudo modprobe nvscic2c-pcie-epc” or “sudo modprobe nvscic2c-pcie-epf” there is no extra pcie log out
2、form the error log “tegra194-pcie 141a0000.pcie: Failed to parse device tree: -517” I think the driver is not ready, so i want to know is the default config correct?
I want to know is there the same error in SDK 6.0.6 on your side, Do you have test nvscic2c-pcie function in SDK 6.0.6? If same error and nvscic2c-pcie can not running OK, I will try to test on 6.0.8.1
Dear @huangxx8,
As I don’t have 2 P3710, I had used only one p3710 as PCIE master and slave. I connected the miniSAS cable port-A to miniSAS port-B in 1 P3710s. Followed the steps from Chip to Chip Communication | NVIDIA Docs