We’re testing pcie compliance.
I add 319ad28_ok.diff and 0001-disabling-the-spread-Spectrum.patch to kernel and dts.
In Gen3 8G test.
In PCIE0 (x4), when we switch preset, the signal will loss in p3, p7 ,p9. But it can switch to p10.
In PCIE2 (x1), when we switch preset, the signal will loss in p3, p7. But it can switch to p10.
In PCIE1 (x1), it can switch to p3.
Update the test pic. In the presets, it has no signal.
Is it an input? What should it be when plug in? It looks like the PCIe device issue of preset?
It’s the output signal from DUT to the scope.
From our experience, it should be like
Hi, are you testing on devkit or custom board? How did you setup the test? Please check the app note and follow the steps in it. Below are the patchs attached in application note, name of yours seems not same.
The following two files are attached to this application note:
319ad28_ok.diff: This file is the patch for disabling power down
9b39010.diff: This file is the patch for disabling the spread Spectrum
In addition, what’s the meaning of “P3, P7 and Px”?
I download Jetson_Orin_NX_Series_Orin_Nano_Series_Tuning_Complinace_Guide_DA-11267-001_v0.9.pdf from download center. And open it with Adobe Acrobat Reader.
There are no 9b39010.diff in the pdf
I will check the test step with our SI engineer.
Yes, you are right. It should be 0001-disabling-the-spread-Spectrum.patch. What’s the meaning of “P3, P7 and Px”?
It means the press times of CBB toggle button in TX test step 8.
When we press the CBB toggle button 3 times(p3) / 7 times(p7) / 9 times (p9) to move PCIE preset, the scope lost signal。
It’s our custom board. But we have same issue on Xavier NX devkit carrier board M.2 M Key PCIE.
Are you sure the patches are applied correctly?
Yes, I check the source code again.
The patchs are applied.
Or how can I check it when system boot?
for the bpmp dtb change, please also check your flash log to make sure that file is correctly flashed.
Yes, in the conf file:
I check bootloader/tegra234-bpmp-3767-0000-a02-3509-a02.dtb file:
clk-id = <0xf3>;
disable-spread = <0x01>;
clk-id = <0x13f>;
disable-spread = <0x01>;
[ 222.9367 ] Writing partition A_bpmp-fw-dtb with tegra234-bpmp-3767-0000-a02-3509-a02_with_odm_sigheader.dtb.encrypt [ 139008 bytes ]
Do you mean board can switch p0, p1, p2, p4…other presets? We don’t meet such issue before. Please share a photo of using toggle on CLB. And per PCIe standard, passing any one of preset (p0-p10) test will pass test.
I mean we use cbb to switch p0~p10 not custom carrier board.
I know it’s pass for PCIE standard.
But we don’t meet this situation on x86(Intel, AMD CPU) before. We can get all signals from p0 to p10.
You said “We don’t meet such issue before.”
So is it a normal case in Orin NX?
If it is, this is solution for this post.
This is our CBB pic. We use the button on the upper left corner to swtich presets.
This video shows signal lost when we press the CBB toggle.
Hi, is there correct100MHz clock when no signal output on some presets?
Yes, the clock is 100MHz.
We are still checking this internally. Will update once available, thanks.
Hi, please see below comments:
If customer didn’t do any changes to PCIe driver, then all presets are enabled for Gen3. They can verify it by dump below registers.
- Clear RATE_SHADOW_SEL in register PCIE_X8_RC_PF0_PORT_LOGIC_GEN3_RELATED_OFF_0
- Read PCIE_X8_RC_PF0_PORT_LOGIC_GEN3_EQ_CONTROL_OFF_0,
GEN3_EQ_PSET_REQ_VEC should be 0x3f
Note: Use setpci on root port BDF to read the register and use respective offset based on the controller used(x1/x4/x8).
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