Question about PCIE reset

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

We have a MINIPCIE connector on our custom JETSON TX2 carrier board.

It work well with a PCIE bus based card.But when with a USB bus based card(a LTE module card) it can not work.
The cause of the problem is the PEX_RST is low after system boot complete.The USB bus based card use the PEX_RST signal as a reset input.
I found that the system power off the pcie controllor when there is no pcie device in the pci-tegra.c

if (!pcie->num_ports) {
	dev_info(pcie->dev, "PCIE: no end points detected\n");
	err = -ENODEV;
	goto fail_power_off;
}

Please give me some suggustions how to let the PEX_RST keep high when thers is no PCIE end points deteted.

2

I don’t know if this is the case for USB based expansions, but I suspect you are seeing a lack of CONFIG_HOTPLUG_PCI being enabled in the kernel config. Check this:

zcat /proc/config.gz | grep HOTPLUG_PCI
3

Thank you！

But we don’t need the HOTPLUG ablilty of the PCIE,and our hardware don’t support the HOT PLUG too.

I connect the PEX1_RST#(pin E50 of the TX2) to the PERST#(PIN 22 of the MINIPCIE socket).

The PEX1_RST# signal set to high when the PCIE controller detect any end point device on the PCIE bus,but set the PEX1_RST# signal to low when there is no end point device can be detected.

When I connect the 4G LTE module (using only the USB bus) to the mini PCIe socket. At this point the PEX1_RST# signal is set to a low level because it does not detect any end-point device. 4G LTE module uses PEX1_RST# as the reset input signal , because the PEX1_RST# has been low level, so the 4G LTE module can not start work normally.

4

Sorry, I can’t help on the custom part. One possibility I can think of is that perhaps a configuration has not been set up at the moment it needs to be in place…but later on the correct configuration won’t matter because detection attempts already occurred. With hot plug it may be that you can retrigger at a later time…the device plugged in would not need to support hot plug, this would (so far as the device is concerned) be cold plug (you aren’t removing and adding the card).

I suggest first adding the HOTPLUG_PCI if for no other reason than to see what happens if you rescan after boot…and look for what the dmesg debug shows up as. This is the easiest thing to test and won’t harm anything or require any device tree change.

Someone else may have a better idea since neither the slot nor the card are used hotplug. I can’t answer the PEX1_RST# question, I lack the knowledge.

5

Thanks！
I am not removing or adding any card after the board power on.
I had add the HOTPLUG_PCI to the kernel,but nothing changed.

6

You can have a patch like below and add “nvidia,disable-power-down” to PCIe node DT entry. This would leave PCIe root port without powering it down when there are no end points detected. Since pex_rst has a pull-up resistor and PCIe is still active, you won’t see pex_rst being driven to ‘0’
Note:- The patch may not cleanly apply, but, basically, this is the idea.

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 2ecc435..c1e28f8 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -468,6 +468,7 @@
 	struct list_head ports;
 	u32 xbar_config;
 	int num_ports;
+	bool disable_power_down;
 
 	int power_rails_enabled;
 	int pcie_power_enabled;
@@ -2510,6 +2511,9 @@
 			tegra_pcie_update_lane_width(port);
 			tegra_pcie_update_pads2plle(port);
 			continue;
+		} else if (pcie->disable_power_down) {
+			port->status = 1;
+			pcie->num_ports++;
 		}
 		port->ep_status = 0;
 		dev_info(pcie->dev, "link %u down, ignoring\n", port->index);
@@ -3417,6 +3421,9 @@
 		pcie->busn.flags = IORESOURCE_BUS;
 	}
 
+	pcie->disable_power_down =
+		of_property_read_bool(np, "nvidia,disable-power-down");
+
 	/* parse root ports */
 	for_each_child_of_node(np, port) {
 		struct tegra_pcie_port *rp;
7

Thank you very much. It’s just what I need.