PCIe WAKE_N signal question

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
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1

Hi,

I am designing my own carrier for Xavier. I am connecting Intel i210 chip to PCIe controller C1 - pcie@14100000. The i210 chip supports WAKE_N function, it will drive WAKE_N pin to zero when it detects a wake event.

I have few questions regarding WAKE_N.

  1. Is WAKE_N optional? Even though i210 chip support WAKE function, can I disable it on host side? If I want to disable it on host side, should I leave WAKE_N pin not connected? Or pull up to 3.3V?

  2. If I want to support WAKE_N on host side for i210, how can I configure it in device-tree? There is only one PEX_WAKE_N (pin A8) signal, but it is already being used by M.2 E key’s WAKE_N signal. Can I pick any unused GPIO? (need 3.3V capable? or thru 1.8V-3.3V conversion). For example, if I choose GPIO18 (pin C55), should I configure device-tree as the following?

pcie@14100000 {
    status = "okay";

    phys = <&p2u_0>;
    phy-names = "pcie-p2u-0";
        
    nvidia,disable-clock-request; // no CLKREQ signal route from i210 to C1
        
    // i210 is GEN2
    nvidia,max-speed = <2>;

    nvidia,pex-wake = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
};
  1. Is GPIO_ACTIVE_HIGH correct? Note I copied it from the device-tree of pcie@14140000 for M.2 E WAKE_N. Should they be set to GPIO_ACTIVE_LOW? Because the WAKE_N is active low. Device (i210) will drive it to zero when detects wake event.

Regards.

5

You can use any wake-capable GPIO as a Wake signal.
I think you can have the routing of that GPIO from the slot (from Intel I210 chip in your case) and whether to enable wake or not can be controlled by having DT entry present or not.
WAKE# is actually an active-low signal, but, let us go with the GPIO_ACTIVE_HIGH itself because of the system configuration.

6

Hi @vidyas

Thanks for your reply.
Unfortunate, we are currently using C55 (GPIO18) which seems not wake-capable GPIO pin, so I need hw change. I want to confirm that are all wake-capable pins marked as wake<wake_number> in the Wake column in pinmux spreadsheet, correct?

I have few more further questions:

  1. Is this wake to wake Xavier from system deep sleep mode, and has nothing to do with runtime pm. I briefly read thru tegra pcie driver, it seems the wake GPIO is used in system suspend (suspend_noirq) and resume (resume_noirq) function of dev_pm_ops, not in the runtime suspend and resume function. So, basically to use this wake feature, user has to put Xavier in system deep sleep mode by sudo systemctl suspend or sudo bash -c "echo mem > /sys/power/state". Then i210 can wake Xavier from deep sleep mode when receiving a packet. Correct?
  2. If “1” is correct, then I think this wake feature is totally an optional feature. i210 will still work, but just not have wake from system deep sleep feature, correct?
  3. Can PEX_WAKE_N be shared? There is only one PEX_WAKE_N, and it is used by M.2 E key’s WAKE_N. I checked devkit schematic, it seems PEX_WAKE_N is shared by x8 PCIe slot and M.2 E on devkit. If PEX_WAKE_N can be shared, I can connect it to i210’s WAKE_N (even though it is connected to M.2 E as well), correct?

Regards.

7

#1 is correct.
#2 is also correct. it is optional in the sense that it is required only if you want the system to have WoL i.e. Wake-on-LAN or WoW i.e. Wake-on-Wireless.
#3. Yes. it is a shared pin.

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