Problem in Frame Start when getting CSI data

Robotics & Edge Computing Jetson & Embedded Systems Jetson Nano
,
1

Hi,
I want to transfer a video data stream from an FPGA board to a Jetson Nano Devkit. I have made some changes in the the ‘imx219’ driver, so now my FPGA board is recognized as ‘/dev/video0’. When I try to capture a test frame using yavta, I get this output and the test frame is never captured.

Device /dev/video0 opened.
Device `vi-output, imx219 7-0010' on `platform:54080000.vi:0' (driver 'tegra-video') supports video, capture, without mplanes.
Video format set: YUYV (56595559) 128x128 (stride 256) field none buffer size 32768
Video format: YUYV (56595559) 128x128 (stride 256) field none buffer size 32768
8 buffers requested.
length: 32768 offset: 0 timestamp type/source: mono/EoF
Buffer 0/0 mapped at address 0x7f834f4000.
length: 32768 offset: 32768 timestamp type/source: mono/EoF
Buffer 1/0 mapped at address 0x7f834cc000.
length: 32768 offset: 65536 timestamp type/source: mono/EoF
Buffer 2/0 mapped at address 0x7f834c4000.
length: 32768 offset: 98304 timestamp type/source: mono/EoF
Buffer 3/0 mapped at address 0x7f834bc000.
length: 32768 offset: 131072 timestamp type/source: mono/EoF
Buffer 4/0 mapped at address 0x7f834b4000.
length: 32768 offset: 163840 timestamp type/source: mono/EoF
Buffer 5/0 mapped at address 0x7f8334f000.
length: 32768 offset: 196608 timestamp type/source: mono/EoF
Buffer 6/0 mapped at address 0x7f83347000.
length: 32768 offset: 229376 timestamp type/source: mono/EoF
Buffer 7/0 mapped at address 0x7f8333f000.

In the kernel outputs I get this error:

[   33.282973] video4linux video0: frame start syncpt timeout!0
[   33.491014] video4linux video0: frame start syncpt timeout!0
[   33.699532] video4linux video0: frame start syncpt timeout!0
[   33.907425] video4linux video0: frame start syncpt timeout!0
[   34.122716] video4linux video0: frame start syncpt timeout!0
[   34.338395] video4linux video0: frame start syncpt timeout!0
[   34.554183] video4linux video0: frame start syncpt timeout!0
[   34.769968] video4linux video0: frame start syncpt timeout!0
[   34.985736] video4linux video0: frame start syncpt timeout!0
[   35.200439] video4linux video0: frame start syncpt timeout!0
[   35.415147] video4linux video0: frame start syncpt timeout!0

Also the contents of the trace file is as follows:

$ sudo cat /sys/kernel/debug/tracing/trace
           yavta-8328  [003] ....  1984.071289: tegra_channel_open: vi-output, imx219 7-0010
           yavta-8328  [000] ....  1984.075182: camera_common_s_power: status : 0x1
           yavta-8328  [000] ....  1984.203159: camera_common_s_power: status : 0x0
           yavta-8328  [000] ....  1984.203588: tegra_channel_set_power: imx219 7-0010 : 0x1
           yavta-8328  [000] ....  1984.203711: camera_common_s_power: status : 0x1
           yavta-8328  [000] ....  1984.227504: tegra_channel_set_power: nvcsi--2 : 0x1
           yavta-8328  [000] ....  1984.227519: csi_s_power: enable : 0x1
 vi-output, imx2-8329  [002] ....  1984.236610: tegra_channel_set_stream: enable : 0x1
 vi-output, imx2-8329  [002] ....  1984.238630: tegra_channel_set_stream: nvcsi--2 : 0x1
 vi-output, imx2-8329  [002] ....  1984.238632: csi_s_stream: enable : 0x1
 vi-output, imx2-8329  [002] ....  1984.238652: tegra_channel_set_stream: imx219 7-0010 : 0x1
 vi-output, imx2-8329  [000] ....  1984.476494: tegra_channel_capture_frame: sof:-270686159872.1
 vi-output, imx2-8329  [000] ....  1984.684493: tegra_channel_capture_frame: sof:-270686171136.1
 vi-output, imx2-8329  [000] ....  1984.892433: tegra_channel_capture_frame: sof:-270686173184.1
 vi-output, imx2-8329  [000] ....  1985.100535: tegra_channel_capture_frame: sof:-270686175232.1
 vi-output, imx2-8329  [000] ....  1985.308633: tegra_channel_capture_frame: sof:-270686174208.1
 vi-output, imx2-8329  [000] ....  1985.516483: tegra_channel_capture_frame: sof:-270686161920.1
 vi-output, imx2-8329  [000] ....  1985.724376: tegra_channel_capture_frame: sof:-270686163968.1
 vi-output, imx2-8329  [000] ....  1985.932485: tegra_channel_capture_frame: sof:-270686166016.1
 vi-output, imx2-8329  [001] ....  1986.140596: tegra_channel_capture_frame: sof:-270686159872.1
 vi-output, imx2-8329  [001] ....  1986.348705: tegra_channel_capture_frame: sof:-270686171136.1
 vi-output, imx2-8329  [003] ....  1986.556690: tegra_channel_capture_frame: sof:-270686173184.1
 vi-output, imx2-8329  [003] ....  1986.764265: tegra_channel_capture_frame: sof:-270686175232.1
 vi-output, imx2-8329  [003] ....  1986.972484: tegra_channel_capture_frame: sof:-270686174208.1
 vi-output, imx2-8329  [003] ....  1987.180470: tegra_channel_capture_frame: sof:-270686161920.1
 vi-output, imx2-8329  [003] ....  1987.388414: tegra_channel_capture_frame: sof:-270686163968.1
 vi-output, imx2-8329  [003] ....  1987.596217: tegra_channel_capture_frame: sof:-270686166016.1
 vi-output, imx2-8329  [003] ....  1987.804482: tegra_channel_capture_frame: sof:-270686159872.1
 vi-output, imx2-8329  [003] ....  1988.012375: tegra_channel_capture_frame: sof:-270686171136.1
 vi-output, imx2-8329  [003] ....  1988.220480: tegra_channel_capture_frame: sof:-270686173184.1
 vi-output, imx2-8329  [003] ....  1988.427939: tegra_channel_capture_frame: sof:-270686175232.1
 vi-output, imx2-8329  [003] ....  1988.636417: tegra_channel_capture_frame: sof:-270686174208.1
 vi-output, imx2-8329  [003] ....  1988.844276: tegra_channel_capture_frame: sof:-270686161920.1
 vi-output, imx2-8329  [003] ....  1989.052192: tegra_channel_capture_frame: sof:-270686163968.1
 vi-output, imx2-8329  [003] ....  1989.260333: tegra_channel_capture_frame: sof:-270686166016.1
 vi-output, imx2-8329  [003] ....  1989.468151: tegra_channel_capture_frame: sof:-270686159872.1
 vi-output, imx2-8329  [003] ....  1989.676115: tegra_channel_capture_frame: sof:-270686171136.1
 vi-output, imx2-8329  [003] ....  1989.884152: tegra_channel_capture_frame: sof:-270686173184.1
 vi-output, imx2-8329  [003] ....  1990.092344: tegra_channel_capture_frame: sof:-270686175232.1
 vi-output, imx2-8329  [003] ....  1990.300320: tegra_channel_capture_frame: sof:-270686174208.1
 vi-output, imx2-8329  [003] ....  1990.508178: tegra_channel_capture_frame: sof:-270686161920.1
 vi-output, imx2-8329  [003] ....  1990.715803: tegra_channel_capture_frame: sof:-270686163968.1
 vi-output, imx2-8329  [003] ....  1990.924002: tegra_channel_capture_frame: sof:-270686166016.1
 vi-output, imx2-8329  [003] ....  1991.132201: tegra_channel_capture_frame: sof:-270686159872.1
           yavta-8328  [001] ....  1991.183926: tegra_channel_close: vi-output, imx219 7-0010
 vi-output, imx2-8329  [003] ....  1991.340264: tegra_channel_capture_frame: sof:-270686171136.1
           yavta-8328  [001] ....  1991.340505: tegra_channel_set_stream: enable : 0x0
           yavta-8328  [001] ....  1991.340511: tegra_channel_set_stream: imx219 7-0010 : 0x0
           yavta-8328  [000] ....  1991.392209: tegra_channel_set_stream: nvcsi--2 : 0x0
           yavta-8328  [000] ....  1991.392226: csi_s_stream: enable : 0x0
           yavta-8328  [000] ....  1991.400237: tegra_channel_set_power: imx219 7-0010 : 0x0
           yavta-8328  [000] ....  1991.400358: camera_common_s_power: status : 0x0
           yavta-8328  [000] ....  1991.400991: tegra_channel_set_power: nvcsi--2 : 0x0
           yavta-8328  [000] ....  1991.400998: csi_s_power: enable : 0x0

I checked CSI signals in the oscilloscope and it seams that signal in both LP and HS modes has correct voltage levels. CSI configuration that I use has 2 lanes and the line rate is 90 Mbps.
I can not find out whether the problem is from the FPGA side or in the linux driver. I would appreciate if anyone can help me on this.

3

Enable the debug message in the csi2_fops.c to check the capture status.

1 Like
4

Hi @ShaneCCC ,
Thank you for your reply. I enabled the debug message and this is the result:

[ 1057.877611] vi 54080000.vi: Calibrate csi port 0
[ 1057.959413] vi 54080000.vi: cil_settingtime was autocalculated
[ 1057.959419] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 1058.188155] video4linux video0: frame start syncpt timeout!0
[ 1058.194458] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[ 1058.194481] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 1058.194499] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 1058.194517] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 1058.194651] vi 54080000.vi: cil_settingtime was autocalculated
[ 1058.194670] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 1058.395488] video4linux video0: frame start syncpt timeout!0
[ 1058.401752] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[ 1058.401774] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 1058.401792] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 1058.401809] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 1058.401943] vi 54080000.vi: cil_settingtime was autocalculated
[ 1058.401961] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[ 1058.603617] video4linux video0: frame start syncpt timeout!0
[ 1058.609910] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[ 1058.609932] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[ 1058.609951] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[ 1058.609968] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[ 1058.610093] vi 54080000.vi: cil_settingtime was autocalculated
[ 1058.610111] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
5

It’s could be the output timing not as MIPI spec. Have a check the CSI_CSI_CILA_STATUS_0 from the TRM from download center.

1 Like
6

Checking CSI_CSI_CILA_STATUS_0 register, I see that these errors are happening:

  • CILA_CLK_LANE_CTRL_ERR
  • CILA_DATA_LANE0_CTRL_ERR
  • CILA_DATA_LANE1_CTRL_ERR

I checked clock and data signals on oscilloscope, they are like this:

clock
clock800×480 105 KB

data
data800×480 106 KB

According to “DSI and CSI Debugging” section of this document, voltage swing of signals in HS mode must be 200 mv :

D-PHY swing for both CSI and DSI should be ~200 mV in high speed mode, with signals
swinging from 100 mV to 300 mV when probed single-endedly. If the swing is 400 mV
(0V to 400 mV), the receiver is not terminating the bus. Check that the receiver side
(NVIDIA ® Tegra ® for CSI and the LCD for DSI) is programmed properly and ready to
accept input.

  1. In my case, I can see that both clock and data line have 400 mv swing. So how can I make sure that the Tegra CSI receiver is programmed correctly?

  2. Also, to avoid signal integrity problems, I have configured CSI transmitter in a low line rate (90 Mbps). I couldn’t find any minimum line rate requirement for Tegra CSI. Can this low line rate make problem?

The CSI transmitter in the FPGA side produces continues clock. So I changed ‘discontinuous_clk’ parameter in the device tree to ‘no’. This is a part of the device tree settings I have set:

				mode0 { 
					mclk_khz = "24000";
					num_lanes = "2";
					tegra_sinterface = "serial_a";
					phy_mode = "DPHY";
					discontinuous_clk = "no";
					dpcm_enable = "false";
					cil_settletime = "0";

					active_w = "128";
					active_h = "128";
					pixel_t = "yuv_yuyv";
					readout_orientation = "90";
					line_length = "128";
					inherent_gain = "1";
					mclk_multiplier = "3.75";
					pix_clk_hz = "182400000";

					gain_factor = "16";
					framerate_factor = "1000000";
					exposure_factor = "1000000";
					min_gain_val = "16"; /* 1.00x */
					max_gain_val = "170"; /* 10.66x */
					step_gain_val = "1";
					default_gain = "16"; /* 1.00x */
					min_hdr_ratio = "1";
					max_hdr_ratio = "1";
					min_framerate = "2000000"; /* 2.0 fps */
					max_framerate = "21000000"; /* 21.0 fps */
					step_framerate = "1";
					default_framerate = "21000000"; /* 21.0 fps */
					min_exp_time = "13"; /* us */
					max_exp_time = "683709"; /* us */
					step_exp_time = "1";
					default_exp_time = "2495"; /* us */

					embedded_metadata_height = "0";
				};

Thanks
Mohammad