Hello!
I downloaded the latest pinmux spreadsheet for TX2, I configured the AUD_MCLK as follows …
Customer Usage: AUD_MCLK
Pin Direction: Output
Req. Initial State: N/A
In the pinmux.dtsi file generated I see …
aud_mclk_pj4 {
nvidia,pins = "aud_mclk_pj4";
nvidia,function = "aud";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
Which looks good. So I don’t see any bugs with the spreadsheet itself. I ran this through the pinmux-dts2cfg.py and get …
$ python pinmux-dts2cfg.py --pinmux addr_info.txt gpio_addr_info.txt por_val.txt --mandatory_pinmux_file mandatory_pinmux.txt tegra18x-jetson-tx2i-tx2-4gb-template-pinmux.dtsi tegra18x-jetson-tx2i-tx2-4gb-template-gpio-default.dtsi 1.0 | grep aud_mclk
pinmux.0x02431020 = 0x00000400; # aud_mclk_pj4: aud, tristate-disable, input-disable, lpdr-disable
Which also looks good. However, I am using the latest version of the pinmux-dts2cfg.py. Which version of L4T are you using? Maybe there is a problem with this script.
With regard to the clock what do you currently have in DT for the sgtl5000 codec? Previously you had the following …
+ /* i2c@31e0000 { */
+ i2c@31e0000 {
+ status = "okay";
+
+ sgtl5000: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&extern1>; /* maybe extern1 ? */
+ micbias-resistor-k-ohms = <2>;
+ micbias-voltage-m-volts = <3000>;
+ VDDA-supply = <&vdd_3v3>;
+ VDDIO-supply = <&vdd_1v8_ap>;
+ status = "okay";
+ };
+ };
This will definitely not work, because you have defined ‘extern1’ as a essentially a pseudo clock. In other words, it does not actually turn on any clock. What you want is …
+ /* i2c@31e0000 { */
+ i2c@31e0000 {
+ status = "okay";
+
+ sgtl5000: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&tegra_car TEGRA186_CLK_AUD_MCLK>;
+ micbias-resistor-k-ohms = <2>;
+ micbias-voltage-m-volts = <3000>;
+ VDDA-supply = <&vdd_3v3>;
+ VDDIO-supply = <&vdd_1v8_ap>;
+ status = "okay";
+ };
+ };
Also when the codec is active you can check if the clock is enabled and what frequency it is operating at by …
$ sudo grep "clock\|aud_mclk" /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate req_rate accuracy phase
aud_mclk 1 1 12287998 12288000 0 0
Regards,
Jon