Problem seeing i2c device on my carrier Please look over my dts changes

Autonomous Machines Jetson & Embedded Systems Jetson TX2
1

Can someone can look over my setup for using a sgtl5000 with i2c on
my carrier board and give some suggestins about what I have missed?

I am running the TX2i on a carrier with a SGTL5000 connected to
i2c-3 (pins C12 and C13 (GP3) also known in the HW manual as Gen9
and in the linux output from i2cdetect as i2c-8)
The i2s hookup is to i2s-2

Following the forum post How can I use Freescale‘s sgtl5000 on TX2？ - Jetson TX2 - NVIDIA Developer Forums

I made the following changes to kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi

diff --git a/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi b/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi
index 12a92ac..31504af 100644
--- a/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi
+++ b/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi
@@ -63,6 +63,31 @@
                status = "okay";
        };
 
+        clocks {
+               sgtl5000_mclk: sgtl5000_mclk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <12288000>;
+                       clock-output-names = "sgtl5000-mclk";
+                       status = "okay";
+               };
+       };
+
+        i2c@31e0000 {
+                status = "okay";
+
+               sgtl5000: sgtl5000@0a {
+                       compatible = "fsl,sgtl5000";
+                       reg = <0x0a>;
+                       clocks = <&sgtl5000_mclk>;
+                       micbias-resistor-k-ohms = <2>;
+                       micbias-voltage-m-volts = <3000>;
+                       VDDA-supply = <&vdd_3v3>;
+                       VDDIO-supply = <&vdd_1v8>;
+                       status = "okay";
+               };
+        };
+
        i2c@3160000 {
                status = "okay";
                lp8557_backlight: lp8557-backlight-s-wuxga-8-0@2c {
@@ -900,8 +925,8 @@
 
                status = "okay";
                lp8557_backlight: lp8557-backlight-s-wuxga-8-0@2c {
@@ -900,8 +925,8 @@
 
                status = "okay";
                nvidia,audio-routing =
-                       "x Headphone",          "x OUT",
-                       "x IN",                 "x Mic",
+                       "x Headphone",          "x HP_OUT",
+                       "x MIC_IN",             "x Mic",
                        "y Headphone",          "y OUT",
                        "y IN",                 "y Mic",
                        "z Headphone",          "z OUT",
@@ -922,12 +947,16 @@
                nvidia,xbar = <&tegra_axbar>;
 
                rt565x_dai_link: nvidia,dai-link-1 {
-                       link-name = "rt565x-playback";
+                       link-name = "fe-pi-audio-z-v2";
                        cpu-dai = <&tegra_i2s1>;
-                       codec-dai = <&spdif_dit0>;
+                       codec-dai = <&sgtl5000>;
                        cpu-dai-name = "I2S1";
-                       codec-dai-name = "dit-hifi";
+                       codec-dai-name = "sgtl5000";
                        format = "i2s";
+                       bitclock-master;  # in example 20190506
+                        frame-master;     #  ditto
+                       bitclock-noninversion; # also was in example - not a change
+                        frame-noninversion;    #also was in example - but not a change
                        bit-format = "s16_le";
                        bclk_ratio = <0>;
                        srate = <48000>;
@@ -940,7 +969,7 @@
                        link-name = "spdif-dit-1";
                        cpu-dai = <&tegra_i2s2>;
                        codec-dai = <&spdif_dit1>;
-                       cpu-dai-name = "I2S2";
+                       cpu-dai-name = "I2S2";      # I2S_2 should be the correct one.
                        codec-dai-name = "dit-hifi";
                        format = "i2s";
                        bit-format = "s16_le";
-- 
2.17.1

I also did the kernel Kconfig and other changes as needed as well as configuring
the modules that were recommended.

However. I think that there must be some low level issue that I missed because
i2cdetect cannot see the sgtl5000 (I have tried both the 0x0a and 0x2a bus
addresses that this chip can be addressed at.) Here is some output showing the
no devices found on i2c-8 (That is the bus that corresponds to the i2c-GP3
name associated with C12 and C13.)

root@aud:~# i2cdetect -l
i2c-3	i2c       	3190000.i2c                     	I2C adapter
i2c-1	i2c       	c240000.i2c                     	I2C adapter
i2c-8	i2c       	31e0000.i2c                     	I2C adapter
i2c-6	i2c       	31c0000.i2c                     	I2C adapter
i2c-4	i2c       	Tegra BPMP I2C adapter          	I2C adapter
i2c-2	i2c       	3180000.i2c                     	I2C adapter
i2c-0	i2c       	3160000.i2c                     	I2C adapter
i2c-7	i2c       	c250000.i2c                     	I2C adapter
i2c-5	i2c       	31b0000.i2c                     	I2C adapter
root@aud:~# i2cdetect -y -r 8
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:          -- -- -- -- -- -- -- -- -- -- -- -- -- 
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
70: -- -- -- -- -- -- -- --                         
root@aud:~#

for comparison the devices on the i2c-PM (bus i2c-7) are found just fine

root@aud:~# i2cdetect -y -r 7

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:          -- -- -- -- -- -- -- -- -- -- -- -- -- 
10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
40: -- -- -- -- -- -- -- -- -- -- -- -- UU -- -- -- 
50: 50 -- -- -- -- -- -- 57 58 -- -- -- -- -- -- -- 
60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 
70: -- -- -- -- -- -- -- --

Obviously the driver isn’t going to work if the device is not even seen.
What did I miss?

Thanks and best regards,

Curtis

2

You may need to probe the TX/RX to check if the device ack first.

3

The sgtl5000 does not appear to ack…

It appears that the clock lines for i2s may be needed for the sgtl5000 to function (I2S_MCLK). I was looking
again at How can I use Freescale&lsquo;s sgtl5000 on TX2？ - Jetson TX2 - NVIDIA Developer Forums
and realized that I had been interrupted before doing the edits to sound/soc/tegra-alt/machine_drivers/tegra_machine_driver_mobile.c

The problem doing those edits it that the soc/tegra-alt directory does not exit in the 4.9 kernel
and doing “grep -R tegra_machine_dai_init” does not find this routine name defined in any file in linux 4.9 under the sound subsystem. I will see what I can learn from the Kconfig files about where the needed driver has gone but would appreciate an tips that would speed the search for the correct driver code to modify in the 4.9 kernel from 32.2.1

Thanks

4

It looks like I should try using CONFIG SND_SOC_TEGRA_SGTL5000 in the 4.9 kernel provided with 32.2.1 can anyone speak to whether that is correct or wrong? The advice in the other post to use SND_SOC_TEGRA_T186REF_MOBILE_ALT appears to only apply to the 4.4 kernel in 28.x

5

The tegra_machine_dai_init is at below patch for r32 release.

…/kernel/nvidia/sound/soc/tegra-alt/machine_drivers/

6

Thanks for the correct path to the code!
After putting the suggested changes in place in the kernel/nvidia/… source area I recompiled and
tested.
I still do not see a clock on pin F1 (AUDIO_MCLK - or AUD_MCLK in the parker manual)
The pin is at a high state after boot and never acts as a clock. That seems to explain why the
SGTL5000 never replies to the i2c.

Are there any examples of setting up the AUD_MCLK in the DTS files. I suspect that is where the
problem is. According to Parker Manual AUD_MCLK can also be named EXTPHERIPH and TOUCH_CLK
and has various settings at 0x520000 0x520004 0x520008 0x521000 0x521004 0x52008 and 0x523000.
I’ll begin searching for those but would really appreciate any info/examples you can add.

7

I am rewriting this last post with my current code changes. It will be complete in a bit.

8

I reread the Nvidia answers to the “How can I use Freescale‘s sgtl5000 on TX2？” post and checked my work. (The Kconfig was already changed in 32.2.1 git pull.) My changes following those instructions are below. The problem is that I do not get the aud_mclk coming out of the TX2i module. It is named extern1 in the stock 32.2.1 audio definition in tegra186-quill-common.dtsi so I attempted to use that name for the sgtl5000 clock definition.

My use of extern1 in the clock definition that was added is (probably) incorrect (sorry I am still a beginner at device tree). Please check the following and point me to an example of a valid clock definition or other help to fix this. The possible existing definitions for the aud_mclk appear to
be the extern1 referenced and clk_aud_mclk_pj4 also is defined and appears to be related.

Thanks very much.

The patches I have made from the instructions and example are as follows:

diff --git a/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi b/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi
index 12a92ac..e4d5c2f 100644
--- a/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi
+++ b/kernel-dts/t18x-common-platforms/tegra186-quill-common.dtsi
@@ -63,6 +63,32 @@
                status = "okay";
        };
 
+        clocks {
+               extern1: extern1 {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <12288000>;
+                       clock-output-names = "extern1";
+                       status = "okay";
+               };
+        };
+
+        /* i2c@31e0000 { */
+       i2c@31e0000 {
+                status = "okay";
+
+               sgtl5000: sgtl5000@0a {
+                       compatible = "fsl,sgtl5000";
+                       reg = <0x0a>;
+                       clocks = <&extern1>;  /* maybe extern1 ? */
+                       micbias-resistor-k-ohms = <2>;
+                       micbias-voltage-m-volts = <3000>;
+                       VDDA-supply = <&vdd_3v3>;
+                       VDDIO-supply = <&vdd_1v8_ap>;
+                       status = "okay";
+               };
+        };
+
        i2c@3160000 {
                status = "okay";
                lp8557_backlight: lp8557-backlight-s-wuxga-8-0@2c {
@@ -900,8 +926,8 @@
 
                status = "okay";
                nvidia,audio-routing =
-                       "x Headphone",          "x OUT",
-                       "x IN",                 "x Mic",
+                       "x Headphone",          "x HP_OUT",
+                       "x MIC_IN",             "x Mic",
                        "y Headphone",          "y OUT",
                        "y IN",                 "y Mic",
                        "z Headphone",          "z OUT",
@@ -922,12 +948,16 @@
                nvidia,xbar = <&tegra_axbar>;
 
                rt565x_dai_link: nvidia,dai-link-1 {
-                       link-name = "rt565x-playback";
-                       cpu-dai = <&tegra_i2s1>;
-                       codec-dai = <&spdif_dit0>;
-                       cpu-dai-name = "I2S1";
-                       codec-dai-name = "dit-hifi";
+                       link-name = "fe-pi-audio-z-v2";
+                       cpu-dai = <&tegra_i2s2>;
+                       codec-dai = <&sgtl5000>;
+                       cpu-dai-name = "I2S2";
+                       codec-dai-name = "sgtl5000";
                        format = "i2s";
+                       bitclock-slave;
+                        frame-slave;
+                       bitclock-noninversion;
+                        frame-noninversion;
                        bit-format = "s16_le";
                        bclk_ratio = <0>;
                        srate = <48000>;

and the machine mobile patch (The Kconfig was already done)

diff --git a/sound/soc/tegra-alt/machine_drivers/tegra_machine_driver_mobile.c b/sound/soc/tegra-alt/machine_drivers/tegra_machine_driver_mobile.c
index cbe8c5ff3..583cc4569 100644
--- a/sound/soc/tegra-alt/machine_drivers/tegra_machine_driver_mobile.c
+++ b/sound/soc/tegra-alt/machine_drivers/tegra_machine_driver_mobile.c
@@ -649,6 +649,29 @@ static int tegra_machine_dai_init(struct snd_soc_pcm_runtime *runtime,
                dai_params->rate_min = clk_rate;
                dai_params->channels_min = channels;
                dai_params->formats = formats;
+                err = snd_soc_dai_set_sysclk(rtd->codec_dai, SGTL5000_SYSCLK,
+                                            clk_out_rate, SND_SOC_CLOCK_IN);
+                if (err) {
+                       dev_err(card->dev, "failed to set sgtl5000 sysclk!\n");
+                       return err;
+               }
+       }
+
+        rtd = snd_soc_get_pcm_runtime(card, "c312_c-audio"); /*sgtl5000 */
+        if (rtd) {
+               dai_params =
+               (struct snd_soc_pcm_stream *)rtd->dai_link->params;
+
+               dai_params->rate_min = clk_rate;
+               dai_params->channels_min = channels;
+               dai_params->formats = formats;
+
+               err = snd_soc_dai_set_sysclk(rtd->codec_dai, SGTL5000_SYSCLK,
+                                            clk_out_rate, SND_SOC_CLOCK_IN);
+               if (err) {
+                       dev_err(card->dev, "failed to set sgtl5000 sysclk!\n");
+                       return err;
+               }
        }
 
        return 0;
@@ -922,6 +945,10 @@ static void dai_link_setup(struct platform_device *pdev)
                                "fe-pi-audio-z-v2")) {
                                tegra_machine_codec_links[i].init =
                                        tegra_machine_fepi_init;
+                       } else if (strstr(tegra_machine_codec_links[i].name,
+                               "c312_c-audio")) {
+                               tegra_machine_codec_links[i].init =
+                                       tegra_machine_fepi_init;
                        }
                }
        }

For reference here is the audio definition including the extern1 clock that is just above the code changes I have made.

#if TEGRA_AUDIO_BUS_DT_VERSION >= DT_VERSION_2
	};
#endif
	hda@3510000 {
		status = "okay";
       };

	tegra_sound: sound {
		compatible = "nvidia,tegra-audio-t186ref-mobile-rt565x";
		nvidia,model = "tegra-snd-t186ref-mobile-rt565x";
		nvidia,num-codec-link = <12>;
		nvidia,num-clk = <8>;
		nvidia,clk-rates = < 270950400	/* PLLA_x11025_RATE */
				     11289600	/* AUD_MCLK_x11025_RATE */
				     45158400	/* PLLA_OUT0_x11025_RATE */
				     45158400	/* AHUB_x11025_RATE */
				     245760000  /* PLLA_x8000_RATE */
				     12288000	/* AUD_MCLK_x8000_RATE */
				     49152000	/* PLLA_OUT0_x8000_RATE */
				     49152000 >;/* AHUB_x8000_RATE */
		clocks = <&tegra_car TEGRA186_CLK_PLLP_OUT0>,
			<&tegra_car TEGRA186_CLK_PLLA>,
			<&tegra_car TEGRA186_CLK_PLL_A_OUT0>,
			<&tegra_car TEGRA186_CLK_AHUB>,
			<&tegra_car TEGRA186_CLK_CLK_M>,
			<&tegra_car TEGRA186_CLK_AUD_MCLK>;
		clock-names = "pll_p_out1", "pll_a", "pll_a_out0", "ahub",
				"clk_m", "extern1";
		resets = <&tegra_car TEGRA186_RESET_AUD_MCLK>;
		reset-names = "extern1_rst";

		status = "okay";
		nvidia,audio-routing =
			"x Headphone",		"x HP_OUT",
			"x MIC_IN",		"x Mic",
9

I just checked the Xavier code changes to see it it would help my understanding of the clock DT code.
I changed the dtsi file as follows. (compiling now - will post results in the morning)

UPDATE: finished compiling and deploying: I still do not get the AUD_MCLK correctly initialized
on pin F1. Please take a look and let me know what else I need to do to get AUD_MCLK correctly
setup for use off of the Tx2i module.

I moved the following down closer to the Audio definitions that got changed. I removed the
clock definition at the same indentation level. Now this code is similar to the code in the
following xavier/sgtl5000 posts (I also modified the sound/soc/tegra-alt/machine_drivers/tegra_machine_driver_mobile.c file to be similar to that post.)

SGTL5000 with Xavier - Jetson AGX Xavier - NVIDIA Developer Forums
Probe of sound failed with error stgl5000 - Jetson AGX Xavier - NVIDIA Developer Forums

   i2c@31e0000 {
	sgtl5000: sgtl5000.8-000a@0a {
	       compatible = "fsl,sgtl5000";
	       reg = <0x0a>;
	       clocks = <&tegra_car TEGRA186_CLK_AUD_MCLK>;
	       clock-names = "extern1";
                   micbias-resistor-k-ohms = <2>;
                   micbias-voltage-m-volts = <3000>;
                   VDDA-supply = <&vdd_3v3>;
                   VDDIO-supply = <&vdd_1v8_ap>;
                   status = "okay";
           };
    };
10

Hello!

A couple notes to begin with …

  1. We have used the FE-PI Audio Z V2 board [0] for testing the SGTL5000 codec and this hardware module has an on-board clock for the codec. So if you are using the AUD_MCLK from Tegra to drive the SGTL5000 MCLK, then yes you will need to specify the clock for the codec as you have listed in comment #9.

  2. L4T r32.2.1 already has support for the FE-PI Audio Z V2 board in the audio machine driver, but because you clock setup is different it may still be necessary to modify the machine driver a bit. However, first we should focus on why the codec is not being detected.

You can share the output from …

$ sudo grep "aud_mclk\|gen9_i2c" /sys/kernel/debug/tegra_pinctrl_reg

This will indicate if the pinmux is correct or not.

Regards,
Jon

[0] https://fe-pi.com/products/fe-pi-audio-z-v2

11

Thanks for taking a look at this Jon.
The result of looking in tegra_pinctrl_reg is:

grep "aud_mclk\|gen9_i2c" /sys/kernel/debug/tegra_pinctrl_reg > for_jon.log
Bank: 0 Reg: 0x02431020 Val: 0x00000059 -> aud_mclk_pj4
Bank: 0 Reg: 0x0243d0c0 Val: 0x00001540 -> gen9_i2c_sda_pl3
Bank: 0 Reg: 0x0243d0c8 Val: 0x00001540 -> gen9_i2c_scl_pl2

I am still trying to figure out how to correlate info from the data sheet, parker manual and dtsi files. does pj4 correspond in some way to pin F1 or are we missing a needed definition?

What is the next step? (Thanks so much for helping me learn to approach fixes to the DTS files)

12

From the Pinmux source it looks like F1 is on GPIO_PJ.04 and that it is first set up as an input with pullup and is disabled. I think I need to revisit this as I do not currently see anywhere this is changed to an output.

Should that change be made with the spreadsheet or fixed later in the other dtsi files?

13

Hello!

Yes it does look like the AUD_MCLK is not configured correctly. The correct way to configure this is to use the pinmux spreadsheet for TX2. The output from the spreadsheet is converted into a cfg file using the pinmux-dts2cfg.py script. See the Linux_for_Tegra/kernel/pinmux/t186/README.txt from the L4T release for more details.

Regards,
Jon

14

Results from my last build:

I might note that the lack of the clock (aud_mclk) is an Nvidia bug that you will want to fix in the pinmux: The TX2 product design guide states that the aud_mclk is an output (Table 58 first line) but the default configuration in the spreadsheet and dtb files provided have set it up as an input. I don’t mind fixing it but could use a little help to make sure I make the correct choices. (ie I used Drive0 but you would need to let me know if Drive1 is possibly a choice more in-line with Nvidia’s intention.)

I went to the pinmux spreadsheet (tx2i page) and changed the values related to aud_mclk from input to output to drive0 and from disabled to enabled. I created the output and ran the python dts2cfg routine and for simplicity copied them over the two files in L4T/bootloader/t186ref/BCT:
tegra186-mb1-bct-pinmux-quill-p3489-1000-a00.cfg
tegra186-mb1-bct-pad-quill-p3489-1000-a00.cfg

grep “aud_mclk” /sys/kernel/debug/tegra_pinctrl_reg now reports

Bank: 0 Reg: 0x02431020 Val: 0x00000101 -> aud_mclk_pj4

But the scope still does not show a clock on pin F1

QUESIONS:

  1. What value should I expect from the grep command?

  2. could the u-boot dtb file in bootloader/t186ref/ be causing the issue?
    (I updated the dts files in the sources/hardware/… area but the dtb files in the
    bootloader directory were not updated by the build. )

  3. Can you give me a pointer to a forum post or nvidia manual that details how to update the
    bootloader and bootloader dtb files in the t186ref directory?

  4. is there something I need to setup for Bank 0 i2c to get them working or does the data below
    validate the current configuration?

I think the i2c pins are OK as the grep for gen9 is the same Val as gen8.

root@aud8a:~# grep "aud_mclk\|gen9_i2c" /sys/kernel/debug/tegra_pinctrl_reg 
Bank: 0 Reg: 0x02431020 Val: 0x00000101 -> aud_mclk_pj4
Bank: 0 Reg: 0x0243d0c0 Val: 0x00001540 -> gen9_i2c_sda_pl3
Bank: 0 Reg: 0x0243d0c8 Val: 0x00001540 -> gen9_i2c_scl_pl2
root@aud8a:~# grep "gen8_i2c" /sys/kernel/debug/tegra_pinctrl_reg 
Bank: 1 Reg: 0x0c302028 Val: 0x00001540 -> gen8_i2c_sda_pw1
Bank: 1 Reg: 0x0c302030 Val: 0x00001540 -> gen8_i2c_scl_pw0

i2cdetect works for gen8 finding connected devices. gen9 still is not seeing the sgtl5000 - not surprizing given the clock is still not functioning.

15

Hello!

As a bit of background, for the Jetson TX2 platform the AUD_MCLK is exposed via the 40-pin expansion header on the platform. This header is modelled on the Raspberry Pi 40-pin header so that it is possible to use HATs such as the FE-PI Audio Z V2 board with Jetson. By default Raspberry Pi configures the pins on the expansion header as GPIO inputs to avoid any signal contention when hardware is connected. For Jetson we do the same and so hence, the AUD_MCLK is not enabled by default. Simply because users may wish to use this pins as a GPIO and not a clock output.

To answer your questions …

  1. The output should look like …

$ sudo grep “aud_mclk|gen9_i2c” /sys/kernel/debug/tegra_pinctrl_reg
Bank: 0 Reg: 0x02431020 Val: 0x00000404 → aud_mclk_pj4
Bank: 0 Reg: 0x0243d0c0 Val: 0x00001440 → gen9_i2c_sda_pl3
Bank: 0 Reg: 0x0243d0c8 Val: 0x00001440 → gen9_i2c_scl_pl2

Note you do not want to set drive-0 or drive-1 as this will drive that state on the pin. Just configure as ‘N/A’ in the spreadsheet to disable the internal pulls. Also you do not have bit 10 set for the AUD_MCLK will still means it is a GPIO. I think that the problem is that you have update the wrong MB1 file which is not obvious indeed!

If you dump the following file you will see the device-tree source version for your TX2 …

$ cat /proc/device-tree/nvidia,dtsfilename                                                                                                                                                                               
/home/jonathanh/workdir/tegra/l4t-rel32/kernel/kernel-4.9/arch/arm64/boot/dts/../../../../../../hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts

The suffix ‘p3310-1000-c03’ is the key here and you need to update the MB1 files that have the same suffix (eg. tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg).

  1. U-Boot should not be a problem for TX2
  2. Updating the bootloader DTB files should not be necessary.
  3. The only difference in your I2C configuration and mine is that you have LPDR bit set, but that you should not be a problem.

By the way, I appreciate that this is a complete pain and we are working to improve this for future releases.

Regards,
Jon

16

Very helpful! Looks like I have a bit of work to do.

Glad to hear that the bootloader DTB will not be an issue as I seem to have problems installing when I modify anything to do with the bootloader. It looks like some kind of signing issue. (I will figure it out later ;-)

On your note about the “suffix P3310”, we are making an industrially hardened product with the TX2i so it is P3489. We are shipping first units very soon so your help is greatly appreciated. It is pretty clear that the right files were changed as the values did change even if the changes were not quite right. I will post the exact setting I change when I redo that so you can critique it properly.

One question: Due to using the TX2i(8 GB) it appears that I should be modifying the third page of the spreadsheet, (Labeled for the TX2i and TX2 4 GB), is that correct?

So to go over the details I need to attend to:

  • I need to redo the spreadsheet and generate the .cfg files.
    this includes drive0 → N/A
    It looks like bit ‘10’ was not set - which configuration is this in the spreadsheet? <------------ One more question
    looks like a change is needed on the definitions of the i2c pins. how do I get from
    0x1540 to 0x1440? Or is that happening due to the dtb loaded by the kernel?

  • Ignore the bootloader. fix the .cfg and dtb as needed and redeploy.

Did that sum it up? (That is what I will be trying.)

Thanks again.

P.S. Here is the filename I use:
cat /proc/device-tree/nvidia,dtsfilename
/media/parvus/DATA/KeithLap/home/keith/WORK/L32.2.H/Linux_for_Tegra/sources/kernel/kernel-4.9/arch/arm64/boot/dts/…/…/…/…/…/…/hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3489-1000-a00-00-base.dts

17

Hello!

Ah, yes OK. To check which MB1 file you need to modify you can check the appropriate *.conf file for the board. For example, if you use the command ‘sudo ./flash jetson-tx2-4GB mmcblk0p1’ to flash the board, then check the jetson-tx2-4GB.conf file to see what file is used for the pinmux.

We need to check on this. I will ask someone to follow-up here.

With regard to bit-10 for the AUD_MCLK, make sure it is set to ‘AUD_MCLK’ under customer usage and not ‘GPIO3_PJ.04’. For the I2C signals to get them from 0x1540 to 0x1440 just set LPDR to disable (although I am not sure this is necessary).

You should only need to update the *.cfg file and not the dtb file.

Regards,
Jon

18

Just to confirm, yes this is correct.

Regards,
Jon

19

Thanks very much for confirming that!
Currently with the LPDR enabled I hear some noise on the sgtl5000 line out when booting but do not have a clock after booting so I will change it to disable. and see if I can find something in the dts files to ensure that the clock gets enabled there for the kernel I’ll also check in the driver. (Definitely no i2c communication yet.) I’m not sure that you can suggest anything helpful from that little piece of info, so I will get back to you when I have a better question for you.

20

I have done a little more testing but still do not get a clock output. (see description of things tried below.) As you can see the changes I made were changing the Audio_mclk set up in the device tree .cfg file. Given I’ve pretty much exhausted the possibilities there Is it possible that the output has been set up properly but that the clock is not clocking? Suggestions on what to check on that would be appreciated.

What I did.
I noticed that when I set up the excel file as mentioned that I get aud_mclk = 401 where you get 404
I think this is a bug in the excel spreadsheet. I found the bit definitions in the Parker manual:
Section 8.31.7.9 PADCTL_AUDIO_AUD_MCLK_0
bit
12 Schmt: 1 to enable (we want 0)
11 Open Drain 1 to enable (want 0 but can try 1 if we set pull up)
10 GPOI_SF_SEL 1 = HSIO 0 = GPIO (We want HSIO)
8 LPDR 1 to enable (want 0 but can try 1)
6 Input 1 to enable (want 0)
4 Tristate 1 to enable (want 0)
3:2 pupd 0=none 1=pull down 2=pullup 3 is reserved (we want 0)
1:0 PM: 0=aud 1 2 and 3 are reserved (we want 0)

Basically it looks like your 404 is HSIO with a pullup (the 401 I got from the spreadsheet
is HSIO + PM=reserved1 which is why I say that the spreadsheet appears to have a bug.)
I gave up on trying to get the specific settings with the spreadsheet and took the last pinmux.cfg I made and edited it directly to get the numbers correct.
Doing that I tried setting:
404 result - no clock (HSIO and pullup)
400 result - no clock (HSIO only)
500 result - no clock (HSIO and LPDR)
C04 result - no clock (HSIO Open drain and pullup)

After trying those it seems likely that the clock itself is not running. There are no other logical setting for the pinmux definition. I am looking at the rest of the Device tree code and the driver to see if there is something I missed. Your suggestions would be appreciated very much as well.

Note: reading the docs the drive0 and drive1 appear to be about drive strength and do not appear to be used to set a state on the pin. Is there a particular drive strength I should set up? (We are only driving one input so I would not expect a loading problem but I will try anything you think will help.)