yes. Please refer to doc/known_issues.md for SPE firmware binary size limitation.
yes. It should run in 256-kilobyte SRAM attached to TCM interface.
yes. It can access shared DRAM. The sample IVC channel implementation exchanges messages through shared memory. Refer to “doc/devicetree-ivc.md” for details.
There are 2 UART ports which SPE R5 can access. Switching R5 debug UART port may need some changes. You can refer to “doc/uart.md” for details.